* New: In cumulus/plugins.block.configuration, added class ConstantsConf
to store information and create instances of "zero" and "one" cells.
Added attribute in BlockConf class.
* Change: In cumulus/plugins.block.configuration, moved the cell cloning
and saving from block.spares.Spares to configuration.BlockConf as
it is a service that can be used by other modules than just spares.
Other modules may modificate the netlists also, like in XXXX.
* Change: In cumulus/plugins.chip.configuration, in various methods,
manage both cases when the layer is symbolic or real (difference
in accessing the underlying BasicLayers).
* Change: In cumulus/plugins.chip.configuration, less clutered display
of lambda length in trace mode (and use of 'L' as 'l' was too close
to '1').
* Bug: In cumulus/plugins.chip.corona.VerticalSide.addBlockages(),
as the clock are now on the *inner* rail(s), blockage must be on
the *outer* rails (power lines).
* New: In cumulus/plugins.chip.pads.Corner, add support for 45 degree
corners (cfg setting "chip.use45corners").
* New: In cumulus/plugins.chip.pads.Side.check(), correct computation
of the side's length. Was using the ioPadStep instead of the pad
cell width!
* Change: In cumulus/plugins.chip.pads.Corona._padAnalysis(), LibreSOCIO
pads uses Verticals for their ring wires (common sense would want
them *Horizontal*). So they must be included in the physical pin
detection, but in turn this cause havoc in pxlib... So create a
filtering according to the library name. This is *not* robust
but will do for now.
* New: In cumulus/plugins.chip.pad.core2chip.CoreToChip, rename
self.state into self.conf for clarity.
New method newEnableForNet(), to create "enable" nets on the
fly for emulated In/Out pads.
As it can edit the netlist (new "enable" nets) call the
BlockConf.rsave() method instead of direct saving through
AllianceFramework.
Raise NotImplementederror instead of ErrorMessage.
* New: In cumulus/plugins.chip.pad.core2chip.IoPad.createPad(),
on emulated In/Out I/O pad like for LibreSOC, generate on the fly
the right enable signal.
If an enable signal is given, it will be used (backward
compatible with the previous behavior).
* New: In cumulus/plugins.chip.pad.core2chip, support for real
LibreSOCIO pads in libresocio.py module.
* New: In cumulus/plugins/core2chip/, support for the FlexLib I/O cells
symbolic abstracts ("niolib"). More flexible way of specifying the
number and positions of the various power pads, both I/O power and
core power.
For niolib (FlexLib I/O abstract), support for multiple clocks,
that is, clock become ordinary pad (with signals typed as CLOCK).
* New: In cumulus/plugins/chip/, added support for niolib and final
integration of multiple clocks (only for niolib).
Note: The previous strategy was not fully coherent in chip mode.
Everything added, net and components must be added at
corona level and not separated between corona and core.
* New: In cumulus/plugins/block.configuration, new FeedsConf object
to handle the feeds and provide a filling area helper.
* New: In cumulus/plugins/block.spares.removeUnusedbuffers() to
remove unused buffers in the pools and replace them by feedthrough.
* Change: In cumulus/plugins.block.spares, unify coordinate/slice
computation. If we are in chip mode, the coordinates are
expressed in the corona *but* aligned on the slices of the
*core* model.
* Change: In cumulus/plugins.block.Block.rsave(), add the '_r' suffix
to the routed cells.
* Change: In cumulus/plugins.clocktree.ClockTree, when in chip mode
create everything at corona level. Also forgot to set type of
clock subnet as clock.
Note: The port is not complete. Integration of LKCL patches will
follow shortly.
* Change: In cumulus/plugins/alpha/block, more simple inheritance
scheme. Use classic inheritance instead of @classdecorator.
BlockConf (renamed from BlockState) now inherit from GaugeConf,
Double inheritance tree, for Block/Chip and BlockConf/ChipConf.
Allow an uniform syntax for configuration parameters.
* New: In cumulus/plugins/alpha/chip, port of the chip plugin and
integrate with the block plugin. It is now a derived class of
Block. ChipConf is also a derived from BlockConf.
Obsolete "./coriolis2/ioring.py", all informations are given
though the ChipConf state class.
* New: In cumulus/plugins/alpha/core2chip, only Alliance/pxlib is
ported yet.
Jean-Paul Chaput