* Change: In cumulus/plugins.block.macro, the METAL2 blockage was
allowing horizontal tracks to be used but the METAL3 blockage
was conflicting with the end of the perpandiculars.
The router was not able to manage that, so we slightly expand
the METAL2 blockage to encompass the unreachable track.
For the same reason, add a METAL4 blockage over METAL2.
* New: In cumulus/plugins.chip.pads, add METAL5 jumpers on all wires
going to/from the I/O pads on the East & West side. This is a
quick hack as:
1. We should put it also on North/South, but no violation
happens here.
2. We should put it on *ouput* wire only (for only those are
connected to transistors gates).
* New: In cumulus/plugins.chip.macro, put jumpers on the East side
connectors for the SRAM block. Also a quick hack, not robust for
anything else than the SRAM.
* Bug: In cumulus/plugins.macro.Macro.__init__(), stick out the rigth number
of pitches on North & East sides (never tested before).
* New: In cumulus/plugins.macro.Macro.__init__(), manage layer change
if the terminal is not in the preferred routing direction. Use BigVia
and put at least two cuts.
* Bug: In cumulus/plugins.block.block.py, always import Python modules
using the exact same path. Otherwise the module may get imported
twice and static variables are duplicated, generating a big mess.
This was causing problem for the LUT in macro.py, and got SRAMs
blocks encapsulated twice.
* New: In cumulus/plugins.block.block.Block.addPlaceHolder(), create
a "place holder" instance over a given area to prevent the placer
from using it. Allow to make space reservation.
* New: In cumulus/plugins.block.configuration.BlockConf, copy the
toXPitch() and toYSlice() methods from spare in order to share
them between modules. Still have to remove some other local copies.
* New: In cumulus/plugins.block.spare.QuadTree, keep a list of all
the X centers of the partitionned areas. For yse by the power lines.
* New: In cumulus/plugins.chip.chip, move doPowerLayout() call from
doChipFloorplan() to doConnectCore(), this is to delay the call
until *after* the spare QuadTree has been created and we can
align the power lines to the centers of the QuadTree.
* New: In cumulus/plugins.chip.pads.Corona.doPowerLayout(), if a
spare QuadTree has been created, align the power lines on the
X center of the leaf areas. This is a cheap way to avoid DRC
errors between the power BigVias and the wires from the various
clock trees (on METAL5).
* New: In cumulus/plugins.block.macro, add an ad-hoc patch for Staf's
SRAMs. The blockage areas are slightly too narrow. We enlarge
them by one pitch.
* Change: In NetBuilder::getPositions(), ordering of source/target points
is now integrated to this function instead of left to the caller.
In case of real (non-symbolic) routing gauge, skrink the ends of
half the wire width.
* Change: In NetBuilderHV::doRp_AutoContacts(), in case of non-METAL1
RoutingPad, put the axis of the segment on the nearest track.
Issue a warning if we have to shift, as it may be a potential
source of routing problems.
* New: Anabatic::Session::getNearestTrackaAxis(), proxy to compute
track positions, knowing the design abutment box.
* Bug: In Katana::PreProcess::propagateCagedConstraints(), when
looking at all the slave components anchoreds on a RoutingPad,
if they do not have an AutoSegment lookup, skip them instead
of crashing.
* New: In cumulus/plugins.block.Block.placeMacro(), new method to
place a macro cell, partly delegating to the Macro block wrapper.
Must be called *after* both core and corona abutment boxes have
been set.
Adjust the macro block position so the METAL2 & METAL3 pins
are exactly on pitch regarding the full routing grid. The reference
being the corona.
A shift, less than one pitch may be applied, leading in some
cases of overlapping abutment boxes. But this shouldn't be a
problem.
The macro to place is designated through a path of instances
names, rooted at the *core* (not the corona). Meaning that the
head instance must be one of the core.
* Change: In cumulus/plugins.chip.Chip, the complete chip I/O pads
plus corona and core placement is moved out from doPnR() and
put into doChipFloorplan(). It is now mandatory to call this
method *before* doPnR().
Those methods are now cleanly separated so we can perform macro
block placement or any inner core floorplaning operations between
them.
* Change: In cumulus/plugins.macro.Macro, instead of creating large
pads for the I/O pins so whatever the block position, they will
be under a grid point, create a simple dogleg to put them on
grid.
To ensure that they are "on grid", the block pins must be
in METAL2 (horizontal E/W) or METAL3 (vertical N/S) and the block
is assumed to be placed so the bottom left corner of it's
abutment box is exactly on one grid point for M2/M3.
This should be done by Block.placeMacro().
* New: In cumulus/plugins.macro.macro.Macro() to encapsulate foreign blocks.
Round their size to an exact number of GCells and a guard of one GCell.
External terminal must be on the periphery and will be made to stick out
in the guard ring. This is sub-optimal for now but provide a workaround
some Katana bad assumptions.
A "perpandicular padding" is also added to terminals to limit the
offgrid related problems. Have to optimize that in conjuction with
Katana.
Jean-Paul Chaput