Placement management:
* Change: In <metis>, always disable the hMetis support regardless of
it being detected or not as the placer is still unable manage the
final bin contents.
Routing gauge management:
* Bug: In CRL Core, <vsclib/alliance.conf>, set the correct pitches and
size for the routing layers and the cell gauge.
* Change: In Katabatic & Kite, extract the correct extension cap for each
routing layer from the layers characteristics (cache then in
Katabatic::Configuration).
* Change: In Katabatic, <AutoSegment>, create segment with the wire width
defined in the gauge. For AutoSegment created on already existing
Segment from the global routing, adjust the width.
* Change: In Katabatic, <AutoSegment>, more accurate information about how
a segment is connected to terminal via source and/or target.
The flag SegStrongTerminal is splitted into SegSourceTerminal and
SegSourceTarget (but still used as a mask). So now we can know by
which end an AutoSegment is connected to a terminal.
* Change: In Katabatic, ::doRp_Access(), create constraint freeing segments
not only when HSmall but also when VSmall (more critical for <vsclib>).
Otherwise we may see AutoSegments with incompatible source/target
constraints.
* Change: In Kite, BuildPowerRails, do not create blockage on PinOnly
layers *but* still create power rails planes. This is a temporary
workaround for <vsclib> where the METAL1 blockages overlaps the
terminals (it was fine for Nero, but they shouldn't for Kite).
* Change: In Kite, <RoutingEvent>, if a TrackSegment is overconstrained,
directly bybass it's slackening state to DataNegociate::Slacken.
Also rename the flag "_canHandleConstraints" to "_overConstrained",
seems clearer to me.
Miscellaneous:
* Change: In CRL Core, <Utilities>, add a "pass-though" capability on the
mstream to temporarily make them print everything.
In CRL Core configuration files, "display.conf", "patterns.conf" and
"technology.conf" share most of their code. So that common part is put
into "common/" and sourced from the final configuration file.
Update the documentation according the the new initialization scheme.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/ : symbolic, the Alliance original one.
* etc/vsc200/ : symbolic, for G. Petley vsclib.
* etc/hcmos9/ : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.
Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
Jean-Paul Chaput