Commit Graph

8 Commits

Author SHA1 Message Date
Jean-Paul Chaput 0b605000ed Bug fixes in Blif parser (no VHDL enforcement) & GDS driver.
* Bug: In Hurricane::DrawingQuery::drawGo(), forgot to apply translation
    on Polygon and Rectilinear.
* Bug: In Hurricane::Rectilinear, forgot implementation of getContour().
    Add a new accessor getPoints().
* Bug: In CRL::Blif::load(), do not always enforce translation towards
    VHDL names. When loading LEF+gds it may change the Cell names between
    the two stages so the gds layout do not get added to the LEF Cell
    phantom.
      Now add a boolean enforceVhdl argument (may be a flag in the future).
* Bug: In ::GdsStream::operator<<(Cell*), forgot to drive the Rectilinear.
2019-03-07 20:14:08 +01:00
Jean-Paul Chaput ea9a1f3710 CRL::Blif parser now able to load both non-Alliance & Alliance design.
* Change: In CRL::Blif, we now can add a list of Hurricane library for
    the parser to look for standart cells. If the library list is *empty*
    we look use the Alliance mechanism, if not, we look *only* in this
    library list. This behavior is implemented in Subckt::createModel(). I
      To add a library, use CRL::Blif::add(Library*).
      This allow to manage symbolic or real mode loading, it may need
    some rework to clarify the interface.
2018-06-08 12:02:49 +02:00
Jean-Paul Chaput 95aba574a5 Happy New Year 2018 ! Update license years... 2018-01-06 17:55:44 +01:00
Jean-Paul Chaput f68ac4d0e6 Argh. cdebug was slowing down the program too much.
* Change: In Hurricane Commons.h, even when cdebug print nothing, it slow
    down the program (three times for Kite!). Create a macro cdebug_log
    which calls cdebug *only* if the debug level is active.
2016-06-11 21:56:12 +02:00
Jean-Paul Chaput 82cff69d9f Complete rewrite of the trace system (now a stream).
* Change: In Hurricane, in Flags add operator overload for "int" type
    and not only "unsigned int". Otherwise the compiler complaints about
    ambiguous overload when using enum values which are considered as
    "int".
      Simpler code for the BaseFlags::contains() method.
      Added implicit conversion from BaseFlags toward bool type.
* Change: In Hurricane, in Commons, complete replacement of the previous
    two trace systems (trace & ltrace) by a stream-based one.
    As it is a true object it is much less fragile than the one based
    on defines (but maybe a little slower).
      Define a reservation table for the trace levels for all the
    Coriolis & Chams components.
* Change: All tools, use the new trace system.
2016-05-17 23:00:06 +02:00
Jean-Paul Chaput 1ef4bc122f Forgot to catch Bug exception. GCell manage 5 terminals of a Net.
* Bug: In Hurricane, in HApplication, ExceptionWidget ans PyHurricane.h,
    forgot to catch the Hurricane::Bug exception which was leading to
    terminate() without explanations.
* Change: In Katabatic, In GCellTopology, now support one GCell with
    five metal1 terminal of the same net. This unlikely configuration
    did appear in the SNX for the first time...
2016-03-17 16:54:53 +01:00
Jean-Paul Chaput 1b7bd9de36 Happy new year 2016! 2016-01-21 00:41:19 +01:00
Jean-Paul Chaput ef9936e87c Support for Net alias names. Blif parser enhancements.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
    Use a structure based on a simple ring of NetAliasHook. The Net
    holds a global map, sorted by names of all the aliases of all Nets.
    Elements NetAliasesHook of the map are slaves of ring whose master
    is an attribute of the Net (it is *not* in the map, as the primary
    name of the Net).
      In case of merge, the aliases of both Nets are merged and the
    name of the merged one become an alias.
      The Cell::getNet() looks in both the Net map and the aliases to
    find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
    configuration files so the real technology is read as early as
    possible to set up the <gridsPerLambda> factor before any lambda
    is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
    has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
    a design into VHDL compliant names (mainly from Blif/Verilog).
    This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
    messages. Align the loading progress information on the other
    parsers.
      Add a capability to select which component of the design will
    be returned, if there are more than one. Use the "." as separator.
    For exemple you can request "Processor.Alu", which will load
    the "Alu" component from the design in "Processor.blif".
      To be able to save a Blif loaded design, systematically convert
    all the name for VHDL compliance, as it is the format used by
    the Coriolis native files (vst).
      Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
    remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
    the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
    Partly redundant with the previous one. Have to better organize
    that later.
2015-04-16 15:40:02 +02:00