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* ./crlcore: 

- New: In tools.configuration.xml, add default values for METAL minimum break
        lengths.
    - Change: In AcmSigda, makes the parser an autonomous one, like for ICCAD or
        ISPD.
    - Change: Remove AcmSigda, Bookshelf and LEF/DEF parsers from the Alliance
        builtins. They are now to be used through import/export.
    - Bug: In Utilities, the <misc.logMode> parameter boolean parameter was used
        the wrong way (true/false).
This commit is contained in:
Jean-Paul Chaput 2010-08-22 12:36:23 +00:00
parent 8a0852c730
commit d0f15b901f
8 changed files with 100 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
crlcore/etc/tools.configuration.xml
View File

@ -75,7 +75,13 @@
<!-- Kite -->
<parameter id="kite.edgeCapacity" type="percentage" value="65" min="0" max="100"/>
<parameter id="kite.expandStep" type="percentage" value="100" min="0" max="100"/>
<parameter id="kite.globalMinBreak" type="int" value="1450"/>
<parameter id="kite.metal1MinBreak" type="int" value="100"/>
<parameter id="kite.metal2MinBreak" type="int" value="100"/>
<parameter id="kite.metal3MinBreak" type="int" value="100"/>
<parameter id="kite.metal4MinBreak" type="int" value="1450"/>
<parameter id="kite.metal5MinBreak" type="int" value="1450"/>
<parameter id="kite.metal6MinBreak" type="int" value="1450"/>
<parameter id="kite.metal7MinBreak" type="int" value="1450"/>
<parameter id="kite.ripupCost" type="int" value="3" min="0"/>
<parameter id="kite.borderRipupLimit" type="int" value="26" min="1"/>
<parameter id="kite.strapRipupLimit" type="int" value="16" min="1"/>
@ -135,9 +141,15 @@
<widget type="title" label="Kite - Detailed Router"/>
<widget id="kite.edgeCapacity" label="Edge Capacity (%)" column="0"/>
<widget id="kite.expandStep" label="Expand Step (%)" column="0"/>
<widget id="kite.globalMinBreak" label="Global Length Min Break" column="0"/>
<widget id="kite.eventsLimit" label="Events Limit" column="0"/>
<widget id="kite.ripupCost" label="Ripup Cost" column="1" spinbox="true"/>
<widget id="kite.metal1MinBreak" label="METAL1 Length Min Break" column="0"/>
<widget id="kite.metal2MinBreak" label="METAL2 Length Min Break" column="0"/>
<widget id="kite.metal3MinBreak" label="METAL3 Length Min Break" column="0"/>
<widget id="kite.metal4MinBreak" label="METAL4 Length Min Break" column="0"/>
<widget id="kite.metal5MinBreak" label="METAL5 Length Min Break" column="0"/>
<widget id="kite.metal6MinBreak" label="METAL6 Length Min Break" column="0"/>
<widget id="kite.metal7MinBreak" label="METAL7 Length Min Break" column="0"/>
<widget type="section" label="Ripup Limits" column="1"/>
<widget id="kite.borderRipupLimit" label="Borders" column="1" spinbox="true"/>
<widget id="kite.strapRipupLimit" label="Straps" column="1" spinbox="true"/>

2
crlcore/src/ccore/AllianceFramework.cpp
View File

@ -192,6 +192,7 @@ namespace CRL {
, DbU::lambda(3) // Via width.
) );
#if 0
routingLayer = technology->getLayer("METAL6");
if ( routingLayer == NULL ) break;
@ -205,7 +206,6 @@ namespace CRL {
, DbU::lambda(2) // Wire width.
, DbU::lambda(3) // Via width.
) );
#if 0
routingLayer = technology->getLayer("METAL7");
if ( routingLayer == NULL ) break;

2
crlcore/src/ccore/CMakeLists.txt
View File

@ -57,6 +57,7 @@
crlcore/DefImport.h
crlcore/DefExport.h
crlcore/LefExport.h
crlcore/AcmSigda.h
crlcore/Iccad04Lefdef.h
crlcore/Ispd04Bookshelf.h
crlcore/Ioc.h
@ -258,6 +259,7 @@
ARGS -d -v -p AcmSigda_ -y ${AcmSigdaParserGrammar} -o ${AcmSigdaParserGrammarCpp}
TARGET AcmSigdaParser
DEPENDS ${AcmSigdaParserScannerCpp}
crlcore/AcmSigda.h
OUTPUTS ${AcmSigdaParserGrammarCpp}
)
include_directories ( ${AcmSigdaParserBinaryDir} )

5
crlcore/src/ccore/ParsersDrivers.cpp
View File

@ -60,8 +60,6 @@
#include "Ap.h"
#include "Vst.h"
#include "Spice.h"
#include "Bookshelf.h"
#include "AcmSigda.h"
#include "openaccess/OpenAccess.h"
@ -219,8 +217,6 @@ namespace CRL {
registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" );
registerSlot ( "oa" , (CellParser_t*)OpenAccess::oaCellParser , "oa" );
//registerSlot ( "oa" , (LibraryParser_t*)OpenAccess::oaLibParser, "oa" );
registerSlot ( "aux" , (CellParser_t*)bookshelfParser, "aux" );
registerSlot ( "bench", (CellParser_t*)acmSigdaParser , "bench" );
}
@ -331,7 +327,6 @@ namespace CRL {
registerSlot ( "ap" , (CellDriver_t*)apDriver , "ap" );
registerSlot ( "vst", (CellDriver_t*)vstDriver , "vst" );
//registerSlot ( "def", (CellDriver_t*)defDriver , "def" );
registerSlot ( "aux", (CellDriver_t*)bookshelfDriver, "test.aux" );
registerSlot ( "spi", (CellDriver_t*)spiceDriver , "spi" );
//registerSlot ( "oa" , (CellDriver_t*)OpenAccess::oaDriver, "oa");
}

4
crlcore/src/ccore/Utilities.cpp
View File

@ -75,8 +75,8 @@ namespace {
void logModeChanged ( Cfg::Parameter* p )
{
if ( p->asBool() ) tty::enable ();
else tty::disable ();
if ( not p->asBool() ) tty::enable ();
else tty::disable ();
}

24
crlcore/src/ccore/acmsigda/AcmSigda.h
View File

@ -1,24 +0,0 @@
#include <string>
namespace Hurricane {
class Cell;
}
#ifndef __ACM_SIGDA_H__
#define __ACM_SIGDA_H__
namespace CRL {
// -------------------------------------------------------------------
// functions.
void acmSigdaParser ( const std::string cellPath, Hurricane::Cell* cell );
}
# endif

50
crlcore/src/ccore/acmsigda/AcmSigdaParserGrammar.yy
View File

@ -20,7 +20,7 @@ using namespace Hurricane;
#include "crlcore/Catalog.h"
#include "crlcore/AllianceFramework.h"
#include "crlcore/NetExtension.h"
#include "AcmSigda.h"
#include "crlcore/AcmSigda.h"
using namespace CRL;
@ -100,6 +100,23 @@ namespace {
}
void addGlobalNets ( Cell* cell )
{
Net* vss = Net::create ( cell, "vss" );
vss->setExternal ( true );
vss->setGlobal ( true );
vss->setType ( Net::Type::GROUND );
Net* vdd = Net::create ( cell, "vdd" );
vdd->setExternal ( true );
vdd->setGlobal ( true );
vdd->setType ( Net::Type::POWER );
Net* ck = getNet ( __state._cell, "ck", Net::Direction::IN, true );
ck->setExternal ( true );
}
Instance* createInstance ();
@ -303,9 +320,11 @@ namespace {
namespace CRL {
void acmSigdaParser ( const string cellPath, Cell *cell )
Cell* AcmSigda::load ( string benchmark )
{
cmess2 << " " << tab << "+ " << cellPath << endl; tab++;
UpdateSession::open ();
cmess2 << " " << tab << "+ " << benchmark << endl; tab++;
static bool firstCall = true;
if ( firstCall ) {
@ -313,11 +332,11 @@ namespace CRL {
__framework = AllianceFramework::get ();
// Preload SxLib using <vst> format.
__framework->getEnvironment()->setIN_LO ( "vst" );
__framework->loadLibraryCells ( "sxlib" );
__framework->getEnvironment()->setIN_LO ( "bench" );
}
Cell* cell = __framework->createCell ( benchmark );
CatalogProperty *sprop =
(CatalogProperty*)cell->getProperty ( CatalogProperty::getPropertyName() );
if ( sprop == NULL )
@ -328,30 +347,21 @@ namespace CRL {
__state._state = sprop->getState();
__state._state->setLogical ( true );
Net* net = getNet ( __state._cell, "vdd", Net::Direction::IN, true );
net->setExternal ( true );
net->setGlobal ( true );
net->setType ( Net::Type::POWER );
addGlobalNets ( cell );
net = getNet ( __state._cell, "vss", Net::Direction::IN, true );
net->setExternal ( true );
net->setGlobal ( true );
net->setType ( Net::Type::GROUND );
net = getNet ( __state._cell, "ck", Net::Direction::IN, true );
net->setExternal ( true );
IoFile ccell ( cellPath );
IoFile ccell ( benchmark+".bench" );
ccell.open ( "r" );
yyin = ccell.getFile ();
if ( not firstCall ) yyrestart ( yyin );
UpdateSession::open ();
yyparse ();
UpdateSession::close ();
ccell.close ();
__state.reset ();
UpdateSession::close ();
return cell;
}

51
crlcore/src/ccore/crlcore/AcmSigda.h Normal file
View File

@ -0,0 +1,51 @@
// -*- C++ -*-
//
// This file is part of the Coriolis Software.
// Copyright (c) UPMC/LIP6 2010-2010, All Rights Reserved
//
// ===================================================================
//
// $Id$
//
// x-----------------------------------------------------------------x
// | |
// | C O R I O L I S |
// | ACM/SIGDA ISCAS 89 Benchmarks |
// | |
// | Author : Jean-Paul CHAPUT |
// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
// | =============================================================== |
// | C++ Header : "./crlcore/AcmSigda.h" |
// | *************************************************************** |
// | U p d a t e s |
// | |
// x-----------------------------------------------------------------x
#ifndef __CRL_ACM_SIGDA__
#define __CRL_ACM_SIGDA__
#include <string>
namespace Hurricane {
class Cell;
}
namespace CRL {
using Hurricane::Cell;
class AcmSigda {
public:
static Cell* load ( std::string benchmark );
};
} // End of CRL namespace.
#endif // __CRL_ACM_SIGDA__