diff --git a/crlcore/etc/tools.configuration.xml b/crlcore/etc/tools.configuration.xml
index 10e00439..3782a5e8 100644
--- a/crlcore/etc/tools.configuration.xml
+++ b/crlcore/etc/tools.configuration.xml
@@ -75,7 +75,13 @@
-
+
+
+
+
+
+
+
@@ -135,9 +141,15 @@
-
+
+
+
+
+
+
+
diff --git a/crlcore/src/ccore/AllianceFramework.cpp b/crlcore/src/ccore/AllianceFramework.cpp
index 2b3c215f..bd8e9565 100644
--- a/crlcore/src/ccore/AllianceFramework.cpp
+++ b/crlcore/src/ccore/AllianceFramework.cpp
@@ -192,6 +192,7 @@ namespace CRL {
, DbU::lambda(3) // Via width.
) );
+#if 0
routingLayer = technology->getLayer("METAL6");
if ( routingLayer == NULL ) break;
@@ -205,7 +206,6 @@ namespace CRL {
, DbU::lambda(2) // Wire width.
, DbU::lambda(3) // Via width.
) );
-#if 0
routingLayer = technology->getLayer("METAL7");
if ( routingLayer == NULL ) break;
diff --git a/crlcore/src/ccore/CMakeLists.txt b/crlcore/src/ccore/CMakeLists.txt
index 4b53b40a..e494a187 100644
--- a/crlcore/src/ccore/CMakeLists.txt
+++ b/crlcore/src/ccore/CMakeLists.txt
@@ -57,6 +57,7 @@
crlcore/DefImport.h
crlcore/DefExport.h
crlcore/LefExport.h
+ crlcore/AcmSigda.h
crlcore/Iccad04Lefdef.h
crlcore/Ispd04Bookshelf.h
crlcore/Ioc.h
@@ -258,6 +259,7 @@
ARGS -d -v -p AcmSigda_ -y ${AcmSigdaParserGrammar} -o ${AcmSigdaParserGrammarCpp}
TARGET AcmSigdaParser
DEPENDS ${AcmSigdaParserScannerCpp}
+ crlcore/AcmSigda.h
OUTPUTS ${AcmSigdaParserGrammarCpp}
)
include_directories ( ${AcmSigdaParserBinaryDir} )
diff --git a/crlcore/src/ccore/ParsersDrivers.cpp b/crlcore/src/ccore/ParsersDrivers.cpp
index d766c292..2ebe9dba 100644
--- a/crlcore/src/ccore/ParsersDrivers.cpp
+++ b/crlcore/src/ccore/ParsersDrivers.cpp
@@ -60,8 +60,6 @@
#include "Ap.h"
#include "Vst.h"
#include "Spice.h"
-#include "Bookshelf.h"
-#include "AcmSigda.h"
#include "openaccess/OpenAccess.h"
@@ -219,8 +217,6 @@ namespace CRL {
registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" );
registerSlot ( "oa" , (CellParser_t*)OpenAccess::oaCellParser , "oa" );
//registerSlot ( "oa" , (LibraryParser_t*)OpenAccess::oaLibParser, "oa" );
- registerSlot ( "aux" , (CellParser_t*)bookshelfParser, "aux" );
- registerSlot ( "bench", (CellParser_t*)acmSigdaParser , "bench" );
}
@@ -331,7 +327,6 @@ namespace CRL {
registerSlot ( "ap" , (CellDriver_t*)apDriver , "ap" );
registerSlot ( "vst", (CellDriver_t*)vstDriver , "vst" );
//registerSlot ( "def", (CellDriver_t*)defDriver , "def" );
- registerSlot ( "aux", (CellDriver_t*)bookshelfDriver, "test.aux" );
registerSlot ( "spi", (CellDriver_t*)spiceDriver , "spi" );
//registerSlot ( "oa" , (CellDriver_t*)OpenAccess::oaDriver, "oa");
}
diff --git a/crlcore/src/ccore/Utilities.cpp b/crlcore/src/ccore/Utilities.cpp
index be114231..dcc1da90 100644
--- a/crlcore/src/ccore/Utilities.cpp
+++ b/crlcore/src/ccore/Utilities.cpp
@@ -75,8 +75,8 @@ namespace {
void logModeChanged ( Cfg::Parameter* p )
{
- if ( p->asBool() ) tty::enable ();
- else tty::disable ();
+ if ( not p->asBool() ) tty::enable ();
+ else tty::disable ();
}
diff --git a/crlcore/src/ccore/acmsigda/AcmSigda.h b/crlcore/src/ccore/acmsigda/AcmSigda.h
deleted file mode 100644
index ef94844c..00000000
--- a/crlcore/src/ccore/acmsigda/AcmSigda.h
+++ /dev/null
@@ -1,24 +0,0 @@
-
-
-#include
-
-
-namespace Hurricane {
- class Cell;
-}
-
-#ifndef __ACM_SIGDA_H__
-#define __ACM_SIGDA_H__
-
-
-namespace CRL {
-
-
-// -------------------------------------------------------------------
-// functions.
-
- void acmSigdaParser ( const std::string cellPath, Hurricane::Cell* cell );
-
-}
-
-# endif
diff --git a/crlcore/src/ccore/acmsigda/AcmSigdaParserGrammar.yy b/crlcore/src/ccore/acmsigda/AcmSigdaParserGrammar.yy
index 40fdd990..6c7e5629 100644
--- a/crlcore/src/ccore/acmsigda/AcmSigdaParserGrammar.yy
+++ b/crlcore/src/ccore/acmsigda/AcmSigdaParserGrammar.yy
@@ -20,7 +20,7 @@ using namespace Hurricane;
#include "crlcore/Catalog.h"
#include "crlcore/AllianceFramework.h"
#include "crlcore/NetExtension.h"
-#include "AcmSigda.h"
+#include "crlcore/AcmSigda.h"
using namespace CRL;
@@ -100,6 +100,23 @@ namespace {
}
+ void addGlobalNets ( Cell* cell )
+ {
+ Net* vss = Net::create ( cell, "vss" );
+ vss->setExternal ( true );
+ vss->setGlobal ( true );
+ vss->setType ( Net::Type::GROUND );
+
+ Net* vdd = Net::create ( cell, "vdd" );
+ vdd->setExternal ( true );
+ vdd->setGlobal ( true );
+ vdd->setType ( Net::Type::POWER );
+
+ Net* ck = getNet ( __state._cell, "ck", Net::Direction::IN, true );
+ ck->setExternal ( true );
+ }
+
+
Instance* createInstance ();
@@ -303,9 +320,11 @@ namespace {
namespace CRL {
- void acmSigdaParser ( const string cellPath, Cell *cell )
+ Cell* AcmSigda::load ( string benchmark )
{
- cmess2 << " " << tab << "+ " << cellPath << endl; tab++;
+ UpdateSession::open ();
+
+ cmess2 << " " << tab << "+ " << benchmark << endl; tab++;
static bool firstCall = true;
if ( firstCall ) {
@@ -313,11 +332,11 @@ namespace CRL {
__framework = AllianceFramework::get ();
// Preload SxLib using format.
- __framework->getEnvironment()->setIN_LO ( "vst" );
__framework->loadLibraryCells ( "sxlib" );
- __framework->getEnvironment()->setIN_LO ( "bench" );
}
+ Cell* cell = __framework->createCell ( benchmark );
+
CatalogProperty *sprop =
(CatalogProperty*)cell->getProperty ( CatalogProperty::getPropertyName() );
if ( sprop == NULL )
@@ -328,30 +347,21 @@ namespace CRL {
__state._state = sprop->getState();
__state._state->setLogical ( true );
- Net* net = getNet ( __state._cell, "vdd", Net::Direction::IN, true );
- net->setExternal ( true );
- net->setGlobal ( true );
- net->setType ( Net::Type::POWER );
+ addGlobalNets ( cell );
- net = getNet ( __state._cell, "vss", Net::Direction::IN, true );
- net->setExternal ( true );
- net->setGlobal ( true );
- net->setType ( Net::Type::GROUND );
-
- net = getNet ( __state._cell, "ck", Net::Direction::IN, true );
- net->setExternal ( true );
-
- IoFile ccell ( cellPath );
+ IoFile ccell ( benchmark+".bench" );
ccell.open ( "r" );
yyin = ccell.getFile ();
if ( not firstCall ) yyrestart ( yyin );
- UpdateSession::open ();
yyparse ();
- UpdateSession::close ();
ccell.close ();
__state.reset ();
+
+ UpdateSession::close ();
+
+ return cell;
}
diff --git a/crlcore/src/ccore/crlcore/AcmSigda.h b/crlcore/src/ccore/crlcore/AcmSigda.h
new file mode 100644
index 00000000..537c090f
--- /dev/null
+++ b/crlcore/src/ccore/crlcore/AcmSigda.h
@@ -0,0 +1,51 @@
+
+// -*- C++ -*-
+//
+// This file is part of the Coriolis Software.
+// Copyright (c) UPMC/LIP6 2010-2010, All Rights Reserved
+//
+// ===================================================================
+//
+// $Id$
+//
+// x-----------------------------------------------------------------x
+// | |
+// | C O R I O L I S |
+// | ACM/SIGDA ISCAS 89 Benchmarks |
+// | |
+// | Author : Jean-Paul CHAPUT |
+// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
+// | =============================================================== |
+// | C++ Header : "./crlcore/AcmSigda.h" |
+// | *************************************************************** |
+// | U p d a t e s |
+// | |
+// x-----------------------------------------------------------------x
+
+
+#ifndef __CRL_ACM_SIGDA__
+#define __CRL_ACM_SIGDA__
+
+#include
+
+namespace Hurricane {
+ class Cell;
+}
+
+
+namespace CRL {
+
+ using Hurricane::Cell;
+
+
+ class AcmSigda {
+ public:
+ static Cell* load ( std::string benchmark );
+ };
+
+
+} // End of CRL namespace.
+
+
+#endif // __CRL_ACM_SIGDA__
+