jcarr
/
coriolis
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Added support for IEEE VHDL in the Vst parser (std_logic). 

* New: In CRL Core, in VstParser, support IEEE VHDL, with tokens
    <library> and <use>. If "use IEEE.std_logic_1164.ALL" is present
    the file will be considered to be IEEE compliant.
      To be precise, the parser now support any mix between Alliance
    and IEEE VHDL. So you can have both <std_logic> and <wor_bit>
    in the same file, but it is unclean to do that.
      The two extensions ".vhd" & ".vhdl" are supported.
      The drivers still always creates Alliance VHDL.
This commit is contained in:
Jean-Paul Chaput 2015-05-10 17:16:00 +02:00
parent 1b79ef75c9
commit 909f86b4fc
4 changed files with 249 additions and 206 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
crlcore/src/LibraryManager/CellsModel.cpp
View File

@ -77,6 +77,14 @@ namespace CRL {
, "VHDL Structural" , "VHDL Structural"
, CellLoader::Native , CellLoader::Native
, Catalog::State::Logical ) ); , Catalog::State::Logical ) );
loaders->addLoader( new CellLoader("vhd"
, "VHDL Structural (IEEE)"
, CellLoader::Native
, Catalog::State::Logical ) );
loaders->addLoader( new CellLoader("vhdl"
, "VHDL Structural (IEEE)"
, CellLoader::Native
, Catalog::State::Logical ) );
loaders->addLoader( new CellLoader("ap" loaders->addLoader( new CellLoader("ap"
, "Alliance Physical" , "Alliance Physical"
, CellLoader::Native , CellLoader::Native

100
crlcore/src/ccore/ParsersDrivers.cpp
View File

@ -1,66 +1,28 @@
// -*- C++ -*- // -*- C++ -*-
// //
// This file is part of the Coriolis Project. // This file is part of the Coriolis Software.
// Copyright (C) Laboratoire LIP6 - Departement ASIM // Copyright (c) UPMC 2008-2015, All Rights Reserved
// Universite Pierre et Marie Curie
// //
// Main contributors : // +-----------------------------------------------------------------+
// Christophe Alexandre <Christophe.Alexandre@lip6.fr>
// Sophie Belloeil <Sophie.Belloeil@lip6.fr>
// Hugo Clément <Hugo.Clement@lip6.fr>
// Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
// Damien Dupuis <Damien.Dupuis@lip6.fr>
// Christian Masson <Christian.Masson@lip6.fr>
// Marek Sroka <Marek.Sroka@lip6.fr>
//
// The Coriolis Project is free software; you can redistribute it
// and/or modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2 of
// the License, or (at your option) any later version.
//
// The Coriolis Project is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with the Coriolis Project; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//
// License-Tag
// Authors-Tag
// ===================================================================
//
// $Id$
//
// x-----------------------------------------------------------------x
// | |
// | C O R I O L I S | // | C O R I O L I S |
// | Alliance / Hurricane Interface | // | Alliance / Hurricane Interface |
// | | // | |
// | Author : Jean-Paul CHAPUT | // | Author : Jean-Paul CHAPUT |
// | E-mail : Jean-Paul.Chaput@asim.lip6.fr | // | E-mail : Jean-Paul.Chaput@lip6.fr |
// | =============================================================== | // | =============================================================== |
// | C++ Module : "./ParserDriver.cpp" | // | C++ Module : "./ParsersDrivers.cpp" |
// | *************************************************************** | // +-----------------------------------------------------------------+
// | U p d a t e s |
// | |
// x-----------------------------------------------------------------x
#include "hurricane/DBo.h"
#include "hurricane/DBo.h" #include "crlcore/Utilities.h"
#include "crlcore/Environment.h"
#include "crlcore/Utilities.h" #include "crlcore/Catalog.h"
#include "crlcore/Environment.h" #include "crlcore/ParsersDrivers.h"
#include "crlcore/Catalog.h" #include "Ap.h"
#include "crlcore/ParsersDrivers.h" #include "Vst.h"
#include "Ap.h" #include "Spice.h"
#include "Vst.h" #include "openaccess/OpenAccess.h"
#include "Spice.h"
#include "openaccess/OpenAccess.h"
namespace { namespace {
@ -74,18 +36,13 @@ namespace {
" Attempt to overwrite registered parser for format \"%s\"\n" " Attempt to overwrite registered parser for format \"%s\"\n"
" and extention \"%s\".\n"; " and extention \"%s\".\n";
} // End of anonymous namespace.
} // Anonymous namespace.
namespace CRL { namespace CRL {
// x-----------------------------------------------------------------x
// | Variables Definitions |
// x-----------------------------------------------------------------x
const char* BadParserType = const char* BadParserType =
"%s:\n\n" "%s:\n\n"
" No registered parser avalaible to load cell \"%s\"\n" " No registered parser avalaible to load cell \"%s\"\n"
@ -104,9 +61,8 @@ namespace CRL {
" (neither logical or physical has been set)\n"; " (neither logical or physical has been set)\n";
// x-----------------------------------------------------------------x // -------------------------------------------------------------------
// | Methods of Class "ParserFormatSlot" | // Class : "ParserFormatSlot"
// x-----------------------------------------------------------------x
bool ParserFormatSlot::cend () { bool ParserFormatSlot::cend () {
@ -203,18 +159,19 @@ namespace CRL {
} }
// x-----------------------------------------------------------------x // -------------------------------------------------------------------
// | Methods of Class "ParsersMap" | // Class : "ParsersMap"
// x-----------------------------------------------------------------x
ParsersMap::ParsersMap (): map<Name,ParserFormatSlot>() ParsersMap::ParsersMap (): map<Name,ParserFormatSlot>()
{ {
// Register the Alliance default parsers. // Register the Alliance default parsers.
registerSlot ( "ap" , (CellParser_t*)apParser , "ap" ); registerSlot ( "ap" , (CellParser_t*)apParser , "ap" );
registerSlot ( "vst" , (CellParser_t*)vstParser , "vst" ); registerSlot ( "vst" , (CellParser_t*)vstParser , "vst" );
registerSlot ( "vst" , (CellParser_t*)vstParser , "vbe" ); registerSlot ( "vst" , (CellParser_t*)vstParser , "vbe" );
registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" ); registerSlot ( "vst" , (CellParser_t*)vstParser , "vhd" );
registerSlot ( "vst" , (CellParser_t*)vstParser , "vhdl" );
registerSlot ( "spi" , (CellParser_t*)spiceParser , "spi" );
registerSlot ( "oa" , (CellParser_t*)OpenAccess::oaCellParser , "oa" ); registerSlot ( "oa" , (CellParser_t*)OpenAccess::oaCellParser , "oa" );
//registerSlot ( "oa" , (LibraryParser_t*)OpenAccess::oaLibParser, "oa" ); //registerSlot ( "oa" , (LibraryParser_t*)OpenAccess::oaLibParser, "oa" );
} }
@ -316,9 +273,8 @@ namespace CRL {
// x-----------------------------------------------------------------x // -------------------------------------------------------------------
// | Methods of Class "DriversMap" | // Class : "DriversMap"
// x-----------------------------------------------------------------x
DriversMap::DriversMap () : map<Name,DriverSlot>() DriversMap::DriversMap () : map<Name,DriverSlot>()

109
crlcore/src/ccore/alliance/vst/VstParserGrammar.yy
View File

@ -1,7 +1,7 @@
%{ %{
// This file is part of the Coriolis Software. // This file is part of the Coriolis Software.
// Copyright (c) UPMC 2008-2014, All Rights Reserved // Copyright (c) UPMC 2008-2015, All Rights Reserved
// //
// +-----------------------------------------------------------------+ // +-----------------------------------------------------------------+
// | C O R I O L I S | // | C O R I O L I S |
@ -67,6 +67,7 @@ namespace Vst {
extern void incVhdLineNumber (); extern void incVhdLineNumber ();
extern void ClearIdentifiers (); extern void ClearIdentifiers ();
void checkForIeee ( bool ieeeEnabled );
class Constraint { class Constraint {
@ -137,6 +138,8 @@ namespace Vst {
bool _masterPort; bool _masterPort;
bool _firstPass; bool _firstPass;
bool _behavioral; bool _behavioral;
bool _ieeeVhdl;
bool _ieeeWarned;
public: public:
YaccState ( const string& vhdFileName ) YaccState ( const string& vhdFileName )
: _vhdFileName (vhdFileName) : _vhdFileName (vhdFileName)
@ -156,6 +159,8 @@ namespace Vst {
, _masterPort (true) , _masterPort (true)
, _firstPass (true) , _firstPass (true)
, _behavioral (false) , _behavioral (false)
, _ieeeVhdl (false)
, _ieeeWarned (false)
{ } { }
bool pushCell ( Name ); bool pushCell ( Name );
}; };
@ -314,6 +319,8 @@ namespace Vst {
%token SEVERITY %token SEVERITY
%token SIGNAL %token SIGNAL
%token _STABLE %token _STABLE
%token STD_LOGIC
%token STD_LOGIC_VECTOR
%token STRING %token STRING
%token SUBTYPE %token SUBTYPE
%token THEN %token THEN
@ -366,10 +373,59 @@ namespace Vst {
%% %%
design_file design_file
: entity_declaration : ...libraries_declarations..
entity_declaration
architecture_body architecture_body
; ;
...libraries_declarations..
: /* Empty */
| library_or_use_statement
...libraries_declarations..
;
library_or_use_statement
: library_statement
| use_statement
;
library_statement
: LIBRARY
Identifier
Semicolon_ERR
;
use_statement
: USE
identifier_path
Semicolon_ERR
{ bool ieeeVhdl = (Vst::states->_identifiersList.size() == 3);
for ( size_t i=0 ; ieeeVhdl and (i<Vst::states->_identifiersList.size()) ; ++i ) {
switch ( i ) {
case 0: if (*(Vst::states->_identifiersList[i]) == "ieee") continue;
case 1: if (*(Vst::states->_identifiersList[i]) == "std_logic_1164") continue;
case 2: if (*(Vst::states->_identifiersList[i]) == "all") continue;
}
ieeeVhdl = false;
break;
}
Vst::states->_ieeeVhdl |= ieeeVhdl;
Vst::states->_identifiersList.clear();
}
;
identifier_path
: path_element
| identifier_path
Dot
path_element
;
path_element
: Identifier { Vst::states->_identifiersList.push_back( $1 ); }
| ALL { Vst::states->_identifiersList.push_back( new string("all") ); }
;
entity_declaration entity_declaration
: ENTITY : ENTITY
.simple_name. .simple_name.
@ -1075,19 +1131,21 @@ type_convertion
; ;
type_mark type_mark
: BIT { $$ = Net::Direction::UNDEFINED; } : BIT { $$ = Net::Direction::UNDEFINED; }
| WOR_BIT { $$ = Net::Direction::ConnWiredOr; } | STD_LOGIC { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(true ); }
| MUX_BIT { $$ = Net::Direction::ConnTristate; } | STD_LOGIC_VECTOR { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(true ); }
| BIT_VECTOR { $$ = Net::Direction::UNDEFINED; } | WOR_BIT { $$ = Net::Direction::ConnWiredOr; Vst::checkForIeee(false); }
| WOR_VECTOR { $$ = Net::Direction::ConnWiredOr; } | MUX_BIT { $$ = Net::Direction::ConnTristate; Vst::checkForIeee(false); }
| MUX_VECTOR { $$ = Net::Direction::ConnTristate; } | BIT_VECTOR { $$ = Net::Direction::UNDEFINED; Vst::checkForIeee(false); }
| INTEGER { $$ = Net::Direction::UNDEFINED; } | WOR_VECTOR { $$ = Net::Direction::ConnWiredOr; Vst::checkForIeee(false); }
| NATURAL { $$ = Net::Direction::UNDEFINED; } | MUX_VECTOR { $$ = Net::Direction::ConnTristate; Vst::checkForIeee(false); }
| NATURAL_VECTOR { $$ = Net::Direction::UNDEFINED; } | INTEGER { $$ = Net::Direction::UNDEFINED; }
| POSITIVE { $$ = Net::Direction::UNDEFINED; } | NATURAL { $$ = Net::Direction::UNDEFINED; }
| STRING { $$ = Net::Direction::UNDEFINED; } | NATURAL_VECTOR { $$ = Net::Direction::UNDEFINED; }
| _LIST { $$ = Net::Direction::UNDEFINED; } | POSITIVE { $$ = Net::Direction::UNDEFINED; }
| ARG { $$ = Net::Direction::UNDEFINED; } | STRING { $$ = Net::Direction::UNDEFINED; }
| _LIST { $$ = Net::Direction::UNDEFINED; }
| ARG { $$ = Net::Direction::UNDEFINED; }
; ;
.BUS. .BUS.
@ -1185,7 +1243,7 @@ namespace Vst {
if ( code < 100 ) if ( code < 100 )
cerr << "[ERROR] CParsVst() VHDL Parser, File:<" << states->_vhdFileName cerr << "[ERROR] CParsVst() VHDL Parser, File:<" << states->_vhdFileName
<< ">, Line:%d" << states->_vhdLineNumber << " Code:" << code << " :\n "; << ">, Line:" << states->_vhdLineNumber << " Code:" << code << " :\n ";
else { else {
if (code < 200) if (code < 200)
cerr << "[ERROR] CParsVst() VHDL Parser, Code:" << code << " :\n "; cerr << "[ERROR] CParsVst() VHDL Parser, Code:" << code << " :\n ";
@ -1224,6 +1282,25 @@ namespace Vst {
} }
// ---------------------------------------------------------------
// Function : "checkForIeee()".
void checkForIeee ( bool ieeeEnabled )
{
if (not states->_ieeeWarned) {
if (ieeeEnabled xor states->_ieeeVhdl) {
states->_ieeeWarned = true;
ostringstream formatted;
formatted << "CParsVst() - VHDL Parser, File:<" << Vst::states->_vhdFileName
<< ">, Line:" << Vst::states->_vhdLineNumber << "\n "
<< "Mixed IEEE VHDL & Alliance VHDL dialects, you should choose one.";
cerr << formatted.str() << endl;
}
}
}
// --------------------------------------------------------------- // ---------------------------------------------------------------
// Function : "getNet()". // Function : "getNet()".

238
crlcore/src/ccore/alliance/vst/VstParserScanner.ll
View File

@ -4,7 +4,7 @@
%{ %{
// This file is part of the Coriolis Software. // This file is part of the Coriolis Software.
// Copyright (c) UPMC 2008-2014, All Rights Reserved // Copyright (c) UPMC 2008-2015, All Rights Reserved
// //
// +-----------------------------------------------------------------+ // +-----------------------------------------------------------------+
// | C O R I O L I S | // | C O R I O L I S |
@ -53,123 +53,125 @@ namespace {
VHDLKeywords::VHDLKeywords () { VHDLKeywords::VHDLKeywords () {
(*this)[ "abs" ] = ABS; (*this)[ "abs" ] = ABS;
(*this)[ "access" ] = ACCESS; (*this)[ "access" ] = ACCESS;
(*this)[ "after" ] = AFTER; (*this)[ "after" ] = AFTER;
(*this)[ "alias" ] = ALIAS; (*this)[ "alias" ] = ALIAS;
(*this)[ "all" ] = ALL; (*this)[ "all" ] = ALL;
(*this)[ "and" ] = tok_AND; (*this)[ "and" ] = tok_AND;
(*this)[ "architecture" ] = ARCHITECTURE; (*this)[ "architecture" ] = ARCHITECTURE;
(*this)[ "arg" ] = ARG; (*this)[ "arg" ] = ARG;
(*this)[ "array" ] = ARRAY; (*this)[ "array" ] = ARRAY;
(*this)[ "assert" ] = ASSERT; (*this)[ "assert" ] = ASSERT;
(*this)[ "attribute" ] = ATTRIBUTE; (*this)[ "attribute" ] = ATTRIBUTE;
(*this)[ "begin" ] = _BEGIN; (*this)[ "begin" ] = _BEGIN;
(*this)[ "bit" ] = BIT; (*this)[ "bit" ] = BIT;
(*this)[ "bit_vector" ] = BIT_VECTOR; (*this)[ "bit_vector" ] = BIT_VECTOR;
(*this)[ "block" ] = BLOCK; (*this)[ "block" ] = BLOCK;
(*this)[ "body" ] = BODY; (*this)[ "body" ] = BODY;
(*this)[ "buffer" ] = BUFFER; (*this)[ "buffer" ] = BUFFER;
(*this)[ "bus" ] = BUS; (*this)[ "bus" ] = BUS;
(*this)[ "case" ] = CASE; (*this)[ "case" ] = CASE;
(*this)[ "component" ] = COMPONENT; (*this)[ "component" ] = COMPONENT;
(*this)[ "configuration" ] = CONFIGURATION; (*this)[ "configuration" ] = CONFIGURATION;
(*this)[ "constant" ] = CONSTANT; (*this)[ "constant" ] = CONSTANT;
(*this)[ "disconnect" ] = DISCONNECT; (*this)[ "disconnect" ] = DISCONNECT;
(*this)[ "downto" ] = DOWNTO; (*this)[ "downto" ] = DOWNTO;
(*this)[ "else" ] = ELSE; (*this)[ "else" ] = ELSE;
(*this)[ "elsif" ] = ELSIF; (*this)[ "elsif" ] = ELSIF;
(*this)[ "end" ] = _END; (*this)[ "end" ] = _END;
(*this)[ "entity" ] = ENTITY; (*this)[ "entity" ] = ENTITY;
(*this)[ "error" ] = ERROR; (*this)[ "error" ] = ERROR;
(*this)[ "exit" ] = _EXIT; (*this)[ "exit" ] = _EXIT;
(*this)[ "file" ] = _FILE; (*this)[ "file" ] = _FILE;
(*this)[ "for" ] = FOR; (*this)[ "for" ] = FOR;
(*this)[ "function" ] = FUNCTION; (*this)[ "function" ] = FUNCTION;
(*this)[ "generate" ] = GENERATE; (*this)[ "generate" ] = GENERATE;
(*this)[ "generic" ] = GENERIC; (*this)[ "generic" ] = GENERIC;
(*this)[ "guarded" ] = GUARDED; (*this)[ "guarded" ] = GUARDED;
(*this)[ "if" ] = IF; (*this)[ "if" ] = IF;
(*this)[ "in" ] = _IN; (*this)[ "in" ] = _IN;
(*this)[ "inout" ] = _INOUT; (*this)[ "inout" ] = _INOUT;
(*this)[ "integer" ] = INTEGER; (*this)[ "integer" ] = INTEGER;
(*this)[ "is" ] = IS; (*this)[ "is" ] = IS;
(*this)[ "label" ] = _LABEL; (*this)[ "label" ] = _LABEL;
(*this)[ "library" ] = LIBRARY; (*this)[ "library" ] = LIBRARY;
(*this)[ "linkage" ] = _LINKAGE; (*this)[ "linkage" ] = _LINKAGE;
(*this)[ "list" ] = _LIST; (*this)[ "list" ] = _LIST;
(*this)[ "loop" ] = LOOP; (*this)[ "loop" ] = LOOP;
(*this)[ "map" ] = MAP; (*this)[ "map" ] = MAP;
(*this)[ "mod" ] = MOD; (*this)[ "mod" ] = MOD;
(*this)[ "mux_bit" ] = MUX_BIT; (*this)[ "mux_bit" ] = MUX_BIT;
(*this)[ "mux_vector" ] = MUX_VECTOR; (*this)[ "mux_vector" ] = MUX_VECTOR;
(*this)[ "nand" ] = _NAND; (*this)[ "nand" ] = _NAND;
(*this)[ "natural" ] = NATURAL; (*this)[ "natural" ] = NATURAL;
(*this)[ "new" ] = NEW; (*this)[ "new" ] = NEW;
(*this)[ "next" ] = _NEXT; (*this)[ "next" ] = _NEXT;
(*this)[ "nor" ] = _NOR; (*this)[ "nor" ] = _NOR;
(*this)[ "not" ] = _NOT; (*this)[ "not" ] = _NOT;
(*this)[ "null" ] = tok_NULL; (*this)[ "null" ] = tok_NULL;
(*this)[ "of" ] = OF; (*this)[ "of" ] = OF;
(*this)[ "on" ] = ON; (*this)[ "on" ] = ON;
(*this)[ "open" ] = OPEN; (*this)[ "open" ] = OPEN;
(*this)[ "or" ] = _OR; (*this)[ "or" ] = _OR;
(*this)[ "others" ] = OTHERS; (*this)[ "others" ] = OTHERS;
(*this)[ "out" ] = _OUT; (*this)[ "out" ] = _OUT;
(*this)[ "package" ] = _PACKAGE; (*this)[ "package" ] = _PACKAGE;
(*this)[ "port" ] = PORT; (*this)[ "port" ] = PORT;
(*this)[ "positive" ] = POSITIVE; (*this)[ "positive" ] = POSITIVE;
(*this)[ "procedure" ] = PROCEDURE; (*this)[ "procedure" ] = PROCEDURE;
(*this)[ "process" ] = PROCESS; (*this)[ "process" ] = PROCESS;
(*this)[ "range" ] = RANGE; (*this)[ "range" ] = RANGE;
(*this)[ "record" ] = RECORD; (*this)[ "record" ] = RECORD;
(*this)[ "reg_bit" ] = REG_BIT; (*this)[ "reg_bit" ] = REG_BIT;
(*this)[ "reg_vector" ] = REG_VECTOR; (*this)[ "reg_vector" ] = REG_VECTOR;
(*this)[ "register" ] = REGISTER; (*this)[ "register" ] = REGISTER;
(*this)[ "rem" ] = REM; (*this)[ "rem" ] = REM;
(*this)[ "report" ] = REPORT; (*this)[ "report" ] = REPORT;
(*this)[ "return" ] = RETURN; (*this)[ "return" ] = RETURN;
(*this)[ "select" ] = SELECT; (*this)[ "select" ] = SELECT;
(*this)[ "severity" ] = SEVERITY; (*this)[ "severity" ] = SEVERITY;
(*this)[ "signal" ] = SIGNAL; (*this)[ "signal" ] = SIGNAL;
(*this)[ "stable" ] = _STABLE; (*this)[ "stable" ] = _STABLE;
(*this)[ "string" ] = STRING; (*this)[ "std_logic" ] = STD_LOGIC;
(*this)[ "subtype" ] = SUBTYPE; (*this)[ "std_logic_vector" ] = STD_LOGIC_VECTOR;
(*this)[ "string" ] = STRING;
(*this)[ "then" ] = THEN; (*this)[ "subtype" ] = SUBTYPE;
(*this)[ "to" ] = TO;
(*this)[ "transport" ] = TRANSPORT; (*this)[ "then" ] = THEN;
(*this)[ "type" ] = _TYPE; (*this)[ "to" ] = TO;
(*this)[ "transport" ] = TRANSPORT;
(*this)[ "units" ] = UNITS; (*this)[ "type" ] = _TYPE;
(*this)[ "until" ] = UNTIL;
(*this)[ "use" ] = USE; (*this)[ "units" ] = UNITS;
(*this)[ "until" ] = UNTIL;
(*this)[ "variable" ] = VARIABLE; (*this)[ "use" ] = USE;
(*this)[ "wait" ] = WAIT; (*this)[ "variable" ] = VARIABLE;
(*this)[ "warning" ] = WARNING;
(*this)[ "when" ] = WHEN; (*this)[ "wait" ] = WAIT;
(*this)[ "while" ] = WHILE; (*this)[ "warning" ] = WARNING;
(*this)[ "with" ] = WITH; (*this)[ "when" ] = WHEN;
(*this)[ "wor_bit" ] = WOR_BIT; (*this)[ "while" ] = WHILE;
(*this)[ "wor_vector" ] = WOR_VECTOR; (*this)[ "with" ] = WITH;
(*this)[ "wor_bit" ] = WOR_BIT;
(*this)[ "xor" ] = _XOR; (*this)[ "wor_vector" ] = WOR_VECTOR;
(*this)[ "xor" ] = _XOR;
} }