jcarr
/
coriolis
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

The VST driver can now be setup to use or not concat ('&') in PORT MAP. 

* New: In CRL::AllianceFramework::saveCell(), through the view flag we
    can pass an option 'CRL::Catalog::State::VstUseConcat' to tell the
    driver tu use or not the concat '&' in PORT MAP statements.
      It is not completely clean that the flag for controlling the VST
    driver behavior is put in the Catalog states, but it's easier for
    now...
      And, of course, exported at Python level.
This commit is contained in:
Jean-Paul Chaput 2019-08-13 14:46:23 +02:00
parent d670de4125
commit 5877691cde
9 changed files with 52 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
crlcore/src/ccore/AllianceFramework.cpp
View File

@ -535,7 +535,7 @@ namespace CRL {
string name = getString(cell->getName());
DriverSlot* driver;
unsigned int saveMode = 0;
unsigned int savedViews = 0;
unsigned int savedViews = mode & (~Catalog::State::Views);
AllianceLibrary* library = getAllianceLibrary ( cell->getLibrary() );
for ( int i=0 ; i<2 ; i++ ) {
@ -548,7 +548,7 @@ namespace CRL {
if ( ( savedViews & saveMode ) != 0 ) continue;
// Transmit all flags except thoses related to views.
saveMode |= (mode & (!Catalog::State::Views));
saveMode |= (mode & (~Catalog::State::Views));
driver = & ( _drivers.getDriverSlot ( name, saveMode, _environment ) );

6
crlcore/src/ccore/alliance/ap/ApDriver.cpp
View File

@ -347,6 +347,12 @@ void DumpPins(ofstream &ccell, Cell* cell)
case Pin::AccessDirection::SOUTH: width = pin->getWidth(); break;
case Pin::AccessDirection::EAST:
case Pin::AccessDirection::WEST: width = pin->getHeight(); break;
default:
cerr << Warning( "CRL::ApDriver(): Pin \"" + getString(pin->getName()) + "\" of \""
+ getString(net->getName())
+ "\", has undefined access direction.")
<< endl;;
break;
}
ccell << "C " << toMBKlambda(pin->getX())

2
crlcore/src/ccore/alliance/vst/VhdlEntity.cpp
View File

@ -402,7 +402,7 @@ namespace Vhdl {
for ( auto isignal=masterSignals->begin() ; isignal!=masterSignals->end() ; ++isignal ) {
if ((*isignal)->isExternal()) {
width = max( width, (*isignal)->getName().size() );
portMaps.push_back( PortMap::create(*isignal) );
portMaps.push_back( PortMap::create(*isignal,_flags) );
portMaps.back()->doMapping( instance );
}
}

19
crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
View File

@ -34,7 +34,8 @@ namespace Vhdl {
// Class : "Vhdl::PortMap".
PortMap::PortMap ()
PortMap::PortMap ( unsigned int flags )
: _flags(flags)
{ }
@ -73,25 +74,25 @@ namespace Vhdl {
}
PortMap* PortMap::create ( const Signal* signal )
PortMap* PortMap::create ( const Signal* signal, unsigned int flags )
{
const ScalarSignal* scalarSignal = dynamic_cast<const ScalarSignal*>( signal );
if (not scalarSignal) {
const VectorSignal* vectorSignal = dynamic_cast<const VectorSignal*>( signal );
if (vectorSignal)
return new VectorPortMap ( vectorSignal );
return new VectorPortMap ( vectorSignal, flags );
else
throw Error( "PortMap::create() Unable to cast toward <ScalarSignal> or <VectorSignal>." );
}
return new ScalarPortMap ( scalarSignal );
return new ScalarPortMap ( scalarSignal, flags );
}
// -------------------------------------------------------------------
// Class : "Vhdl::ScalarPortMap".
ScalarPortMap::ScalarPortMap ( const ScalarSignal* signal )
: PortMap ()
ScalarPortMap::ScalarPortMap ( const ScalarSignal* signal, unsigned int flags )
: PortMap (flags)
, _signal (signal)
, _mapping(NULL)
{ }
@ -120,8 +121,8 @@ namespace Vhdl {
// -------------------------------------------------------------------
// Class : "Vhdl::VectorPortMap".
VectorPortMap::VectorPortMap ( const VectorSignal* signal )
: PortMap ()
VectorPortMap::VectorPortMap ( const VectorSignal* signal, unsigned int flags )
: PortMap (flags)
, _signal (signal)
, _mapping()
{
@ -222,7 +223,7 @@ namespace Vhdl {
}
}
if (mappedNames.size() == 1) {
if ( (mappedNames.size() == 1) or (_flags & Entity::VstUseConcat) ) {
out << setw(width) << left << _signal->getName() << " => ";
size_t lhsWidth = 90 - tab.getWidth() - width - 4;

10
crlcore/src/ccore/alliance/vst/VstDriver.cpp
View File

@ -36,13 +36,13 @@ namespace CRL {
using namespace std;
void vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState )
void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState )
{
unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
if (saveState & Catalog::State::VstUseConcat) entityFlags |= Vhdl::Entity::VstUseConcat;
//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell
, Vhdl::Entity::EntityMode
//| Vhdl::Entity::IeeeMode
);
Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
string celltest = cellPath;
ofstream ccelltest ( celltest.c_str() );

1
crlcore/src/ccore/crlcore/Catalog.h
View File

@ -85,6 +85,7 @@ namespace CRL {
, Physical = 1 << 6
, InMemory = 1 << 7
, Foreign = 1 << 8
, VstUseConcat = 1 << 9
, Views = Physical|Logical
};
// Constructors.

1
crlcore/src/ccore/crlcore/VhdlEntity.h
View File

@ -64,6 +64,7 @@ namespace Vhdl {
, ComponentMode = 0x0004
, AsPortSignal = 0x0008
, AsInnerSignal = 0x0010
, VstUseConcat = 0x0020
};
public:
static std::vector<Entity*>&

10
crlcore/src/ccore/crlcore/VhdlPortMap.h
View File

@ -35,14 +35,16 @@ namespace Vhdl {
class PortMap {
public:
static PortMap* create ( const Signal* );
static PortMap* create ( const Signal*, unsigned int flags );
virtual const Signal* getSignal () const = 0;
virtual void doMapping ( Instance* ) = 0;
virtual void toVhdlPortMap ( std::ostream&, size_t ) const = 0;
PortMap ();
PortMap ( unsigned int flags );
virtual ~PortMap ();
protected:
static const Bit* _lookup ( const Bit* masterBit, Instance* );
protected:
unsigned int _flags;
};
@ -51,7 +53,7 @@ namespace Vhdl {
class ScalarPortMap : public PortMap {
public:
ScalarPortMap ( const ScalarSignal* );
ScalarPortMap ( const ScalarSignal*, unsigned int flags );
virtual ~ScalarPortMap ();
virtual const ScalarSignal* getSignal () const;
virtual void doMapping ( Instance* );
@ -67,7 +69,7 @@ namespace Vhdl {
class VectorPortMap : public PortMap {
public:
VectorPortMap ( const VectorSignal* );
VectorPortMap ( const VectorSignal*, unsigned int flags );
virtual ~VectorPortMap ();
virtual const VectorSignal* getSignal () const;
virtual void doMapping ( Instance* );

4
crlcore/src/pyCRL/PyCatalogState.cpp
View File

@ -136,13 +136,15 @@ extern "C" {
{
PyObject* constant;
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::FlattenLeaf,"FlattenLeaf");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::FlattenLeaf ,"FlattenLeaf");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Feed ,"Feed");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::GDS ,"GDS");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Delete ,"Delete");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Logical ,"Logical");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Physical ,"Physical");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::InMemory ,"InMemory");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat,"VstUseConcat");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views");
}