From 5877691cde65ee59881dd9e2bf0d38f4726830a8 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Tue, 13 Aug 2019 14:46:23 +0200 Subject: [PATCH] The VST driver can now be setup to use or not concat ('&') in PORT MAP. * New: In CRL::AllianceFramework::saveCell(), through the view flag we can pass an option 'CRL::Catalog::State::VstUseConcat' to tell the driver tu use or not the concat '&' in PORT MAP statements. It is not completely clean that the flag for controlling the VST driver behavior is put in the Catalog states, but it's easier for now... And, of course, exported at Python level. --- crlcore/src/ccore/AllianceFramework.cpp | 4 ++-- crlcore/src/ccore/alliance/ap/ApDriver.cpp | 6 ++++++ crlcore/src/ccore/alliance/vst/VhdlEntity.cpp | 2 +- .../src/ccore/alliance/vst/VhdlPortMap.cpp | 19 +++++++++-------- crlcore/src/ccore/alliance/vst/VstDriver.cpp | 10 ++++----- crlcore/src/ccore/crlcore/Catalog.h | 21 ++++++++++--------- crlcore/src/ccore/crlcore/VhdlEntity.h | 1 + crlcore/src/ccore/crlcore/VhdlPortMap.h | 10 +++++---- crlcore/src/pyCRL/PyCatalogState.cpp | 18 +++++++++------- 9 files changed, 52 insertions(+), 39 deletions(-) diff --git a/crlcore/src/ccore/AllianceFramework.cpp b/crlcore/src/ccore/AllianceFramework.cpp index 002ef208..7a5ee931 100644 --- a/crlcore/src/ccore/AllianceFramework.cpp +++ b/crlcore/src/ccore/AllianceFramework.cpp @@ -535,7 +535,7 @@ namespace CRL { string name = getString(cell->getName()); DriverSlot* driver; unsigned int saveMode = 0; - unsigned int savedViews = 0; + unsigned int savedViews = mode & (~Catalog::State::Views); AllianceLibrary* library = getAllianceLibrary ( cell->getLibrary() ); for ( int i=0 ; i<2 ; i++ ) { @@ -548,7 +548,7 @@ namespace CRL { if ( ( savedViews & saveMode ) != 0 ) continue; // Transmit all flags except thoses related to views. - saveMode |= (mode & (!Catalog::State::Views)); + saveMode |= (mode & (~Catalog::State::Views)); driver = & ( _drivers.getDriverSlot ( name, saveMode, _environment ) ); diff --git a/crlcore/src/ccore/alliance/ap/ApDriver.cpp b/crlcore/src/ccore/alliance/ap/ApDriver.cpp index c7ccc1f1..64379b6a 100644 --- a/crlcore/src/ccore/alliance/ap/ApDriver.cpp +++ b/crlcore/src/ccore/alliance/ap/ApDriver.cpp @@ -347,6 +347,12 @@ void DumpPins(ofstream &ccell, Cell* cell) case Pin::AccessDirection::SOUTH: width = pin->getWidth(); break; case Pin::AccessDirection::EAST: case Pin::AccessDirection::WEST: width = pin->getHeight(); break; + default: + cerr << Warning( "CRL::ApDriver(): Pin \"" + getString(pin->getName()) + "\" of \"" + + getString(net->getName()) + + "\", has undefined access direction.") + << endl;; + break; } ccell << "C " << toMBKlambda(pin->getX()) diff --git a/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp b/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp index 8ee28c1d..a978db12 100644 --- a/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp +++ b/crlcore/src/ccore/alliance/vst/VhdlEntity.cpp @@ -402,7 +402,7 @@ namespace Vhdl { for ( auto isignal=masterSignals->begin() ; isignal!=masterSignals->end() ; ++isignal ) { if ((*isignal)->isExternal()) { width = max( width, (*isignal)->getName().size() ); - portMaps.push_back( PortMap::create(*isignal) ); + portMaps.push_back( PortMap::create(*isignal,_flags) ); portMaps.back()->doMapping( instance ); } } diff --git a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp index 99e1db48..b85324b4 100644 --- a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp +++ b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp @@ -34,7 +34,8 @@ namespace Vhdl { // Class : "Vhdl::PortMap". - PortMap::PortMap () + PortMap::PortMap ( unsigned int flags ) + : _flags(flags) { } @@ -73,25 +74,25 @@ namespace Vhdl { } - PortMap* PortMap::create ( const Signal* signal ) + PortMap* PortMap::create ( const Signal* signal, unsigned int flags ) { const ScalarSignal* scalarSignal = dynamic_cast( signal ); if (not scalarSignal) { const VectorSignal* vectorSignal = dynamic_cast( signal ); if (vectorSignal) - return new VectorPortMap ( vectorSignal ); + return new VectorPortMap ( vectorSignal, flags ); else throw Error( "PortMap::create() Unable to cast toward or ." ); } - return new ScalarPortMap ( scalarSignal ); + return new ScalarPortMap ( scalarSignal, flags ); } // ------------------------------------------------------------------- // Class : "Vhdl::ScalarPortMap". - ScalarPortMap::ScalarPortMap ( const ScalarSignal* signal ) - : PortMap () + ScalarPortMap::ScalarPortMap ( const ScalarSignal* signal, unsigned int flags ) + : PortMap (flags) , _signal (signal) , _mapping(NULL) { } @@ -120,8 +121,8 @@ namespace Vhdl { // ------------------------------------------------------------------- // Class : "Vhdl::VectorPortMap". - VectorPortMap::VectorPortMap ( const VectorSignal* signal ) - : PortMap () + VectorPortMap::VectorPortMap ( const VectorSignal* signal, unsigned int flags ) + : PortMap (flags) , _signal (signal) , _mapping() { @@ -222,7 +223,7 @@ namespace Vhdl { } } - if (mappedNames.size() == 1) { + if ( (mappedNames.size() == 1) or (_flags & Entity::VstUseConcat) ) { out << setw(width) << left << _signal->getName() << " => "; size_t lhsWidth = 90 - tab.getWidth() - width - 4; diff --git a/crlcore/src/ccore/alliance/vst/VstDriver.cpp b/crlcore/src/ccore/alliance/vst/VstDriver.cpp index c5bfbb1e..8fb670ff 100644 --- a/crlcore/src/ccore/alliance/vst/VstDriver.cpp +++ b/crlcore/src/ccore/alliance/vst/VstDriver.cpp @@ -36,13 +36,13 @@ namespace CRL { using namespace std; - void vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState ) + void vstDriver ( const string cellPath, Cell *cell, unsigned int& saveState ) { + unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */; + if (saveState & Catalog::State::VstUseConcat) entityFlags |= Vhdl::Entity::VstUseConcat; + //NamingScheme::toVhdl( cell, NamingScheme::FromVerilog ); - Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell - , Vhdl::Entity::EntityMode - //| Vhdl::Entity::IeeeMode - ); + Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags ); string celltest = cellPath; ofstream ccelltest ( celltest.c_str() ); diff --git a/crlcore/src/ccore/crlcore/Catalog.h b/crlcore/src/ccore/crlcore/Catalog.h index e9b02748..09329cf0 100644 --- a/crlcore/src/ccore/crlcore/Catalog.h +++ b/crlcore/src/ccore/crlcore/Catalog.h @@ -76,16 +76,17 @@ namespace CRL { class State { public: // Flags Constants. - enum Flags { FlattenLeaf = 1 << 0 - , Feed = 1 << 1 - , Pad = 1 << 2 - , GDS = 1 << 3 - , Delete = 1 << 4 - , Logical = 1 << 5 - , Physical = 1 << 6 - , InMemory = 1 << 7 - , Foreign = 1 << 8 - , Views = Physical|Logical + enum Flags { FlattenLeaf = 1 << 0 + , Feed = 1 << 1 + , Pad = 1 << 2 + , GDS = 1 << 3 + , Delete = 1 << 4 + , Logical = 1 << 5 + , Physical = 1 << 6 + , InMemory = 1 << 7 + , Foreign = 1 << 8 + , VstUseConcat = 1 << 9 + , Views = Physical|Logical }; // Constructors. inline State (); diff --git a/crlcore/src/ccore/crlcore/VhdlEntity.h b/crlcore/src/ccore/crlcore/VhdlEntity.h index ddd41e09..015515ec 100644 --- a/crlcore/src/ccore/crlcore/VhdlEntity.h +++ b/crlcore/src/ccore/crlcore/VhdlEntity.h @@ -64,6 +64,7 @@ namespace Vhdl { , ComponentMode = 0x0004 , AsPortSignal = 0x0008 , AsInnerSignal = 0x0010 + , VstUseConcat = 0x0020 }; public: static std::vector& diff --git a/crlcore/src/ccore/crlcore/VhdlPortMap.h b/crlcore/src/ccore/crlcore/VhdlPortMap.h index 0ca2570b..d8f74dd9 100644 --- a/crlcore/src/ccore/crlcore/VhdlPortMap.h +++ b/crlcore/src/ccore/crlcore/VhdlPortMap.h @@ -35,14 +35,16 @@ namespace Vhdl { class PortMap { public: - static PortMap* create ( const Signal* ); + static PortMap* create ( const Signal*, unsigned int flags ); virtual const Signal* getSignal () const = 0; virtual void doMapping ( Instance* ) = 0; virtual void toVhdlPortMap ( std::ostream&, size_t ) const = 0; - PortMap (); + PortMap ( unsigned int flags ); virtual ~PortMap (); protected: static const Bit* _lookup ( const Bit* masterBit, Instance* ); + protected: + unsigned int _flags; }; @@ -51,7 +53,7 @@ namespace Vhdl { class ScalarPortMap : public PortMap { public: - ScalarPortMap ( const ScalarSignal* ); + ScalarPortMap ( const ScalarSignal*, unsigned int flags ); virtual ~ScalarPortMap (); virtual const ScalarSignal* getSignal () const; virtual void doMapping ( Instance* ); @@ -67,7 +69,7 @@ namespace Vhdl { class VectorPortMap : public PortMap { public: - VectorPortMap ( const VectorSignal* ); + VectorPortMap ( const VectorSignal*, unsigned int flags ); virtual ~VectorPortMap (); virtual const VectorSignal* getSignal () const; virtual void doMapping ( Instance* ); diff --git a/crlcore/src/pyCRL/PyCatalogState.cpp b/crlcore/src/pyCRL/PyCatalogState.cpp index a7f969c2..26a41f8d 100644 --- a/crlcore/src/pyCRL/PyCatalogState.cpp +++ b/crlcore/src/pyCRL/PyCatalogState.cpp @@ -136,14 +136,16 @@ extern "C" { { PyObject* constant; - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::FlattenLeaf,"FlattenLeaf"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Feed ,"Feed"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::GDS ,"GDS"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Delete ,"Delete"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Logical ,"Logical"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Physical ,"Physical"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::InMemory ,"InMemory"); - LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::FlattenLeaf ,"FlattenLeaf"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Feed ,"Feed"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::GDS ,"GDS"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Delete ,"Delete"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Logical ,"Logical"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Physical ,"Physical"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::InMemory ,"InMemory"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat,"VstUseConcat"); + LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views"); }