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* <All Tools>/CMakeLists.txt: 

- Bug: During the packaging stage, DESTDIR must be appended to the
        pathes prepended to CMAKE_MODULE_PATH.
  * ./stratus:
    - Bug: In dpgen_RF1.py, small typo for the python executable if the module
        is to be run stand-alone. Never show in normal uses.
    - Bug: In ROM_encours & dpen_ROM, correct bad indentation.
This commit is contained in:
Jean-Paul Chaput 2011-02-02 11:44:55 +00:00
parent 7108bc716b
commit 4d18ce2d10
4 changed files with 32 additions and 32 deletions
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2
stratus1/CMakeLists.txt
View File

@ -4,7 +4,7 @@
option(BUILD_DOC "Build the documentation (latex2html)" OFF) option(BUILD_DOC "Build the documentation (latex2html)" OFF)
cmake_minimum_required(VERSION 2.4.0) cmake_minimum_required(VERSION 2.4.0)
list(INSERT CMAKE_MODULE_PATH 0 "$ENV{BOOTSTRAP_TOP}/share/cmake/Modules/") list(INSERT CMAKE_MODULE_PATH 0 "${DESTDIR}/$ENV{BOOTSTRAP_TOP}/share/cmake/Modules/")
find_package(Bootstrap REQUIRED) find_package(Bootstrap REQUIRED)
setup_project_paths(VLSISAPD) setup_project_paths(VLSISAPD)
setup_project_paths(CORIOLIS) setup_project_paths(CORIOLIS)

34
stratus1/src/dpgen/ROM_encours.py
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@ -148,30 +148,30 @@ class dpgen_ROM ( Model ) :
# #
# dpgen_ROM_code ( LV_name, nbit, nword, 0, 0, data ) # !!! # dpgen_ROM_code ( LV_name, nbit, nword, 0, 0, data ) # !!!
for i in range ( nbit ) : for i in range ( nbit ) :
if i % 4 == 0 : if i % 4 == 0 :
cellin = "rom_data_invss" cellin = "rom_data_invss"
cellmid = "rom_data_midvss" cellmid = "rom_data_midvss"
cellout = "rom_data_outvss" cellout = "rom_data_outvss"
elif i % 4 == 1 : elif i % 4 == 1 :
cellin = "rom_data_insel" cellin = "rom_data_insel"
cellmid = "rom_data_midsel" cellmid = "rom_data_midsel"
cellout = "rom_data_outsel" cellout = "rom_data_outsel"
elif i % 4 == 2: elif i % 4 == 2:
cellin = "rom_data_insel" cellin = "rom_data_insel"
cellmid = "rom_data_midsel" cellmid = "rom_data_midsel"
cellout = "rom_data_outsel" cellout = "rom_data_outsel"
elif i % 4 == 3 : elif i % 4 == 3 :
cellin = "rom_data_invss" cellin = "rom_data_invss"
cellmid = "rom_data_midvss" cellmid = "rom_data_midvss"
cellout = "rom_data_outvss" cellout = "rom_data_outvss"
instanciate ( cellin instanciate ( cellin
, "in%d" % i , "in%d" % i

2
stratus1/src/dpgen/dpgen_RF1.py
View File

@ -1,4 +1,4 @@
#!/usr/bin/pythn #!/usr/bin/python
# This file is part of the Coriolis Project. # This file is part of the Coriolis Project.
# Copyright (C) Laboratoire LIP6 - Departement ASIM # Copyright (C) Laboratoire LIP6 - Departement ASIM

12
stratus1/src/dpgen/dpgen_ROM.py
View File

@ -416,12 +416,12 @@ class TopRom ( Model ) :
, 'vdd' : self.vdd , 'vdd' : self.vdd
, 'vss' : self.vss , 'vss' : self.vss
} }
if self.nword != 64 : thisMap['col'] = col[j] if self.nword != 64 : thisMap['col'] = col[j]
else : thisMap['col'] = One ( 1 ) else : thisMap['col'] = One ( 1 )
And23[j] = Inst ( "rom_dec_line23" And23[j] = Inst ( "rom_dec_line23"
, "and23_%d" % j , "and23_%d" % j
, map = thisMap , map = thisMap
) )
if type == 0 : model = "rom_dec_selmux23" if type == 0 : model = "rom_dec_selmux23"
else : model = "rom_dec_selmux23_rs" else : model = "rom_dec_selmux23_rs"