diff --git a/stratus1/CMakeLists.txt b/stratus1/CMakeLists.txt
index c0a34cb4..a1baa089 100644
--- a/stratus1/CMakeLists.txt
+++ b/stratus1/CMakeLists.txt
@@ -4,7 +4,7 @@
  option(BUILD_DOC "Build the documentation (latex2html)" OFF)
 
  cmake_minimum_required(VERSION 2.4.0)
- list(INSERT CMAKE_MODULE_PATH 0 "$ENV{BOOTSTRAP_TOP}/share/cmake/Modules/")
+ list(INSERT CMAKE_MODULE_PATH 0 "${DESTDIR}/$ENV{BOOTSTRAP_TOP}/share/cmake/Modules/")
  find_package(Bootstrap REQUIRED)
  setup_project_paths(VLSISAPD)
  setup_project_paths(CORIOLIS)
diff --git a/stratus1/src/dpgen/ROM_encours.py b/stratus1/src/dpgen/ROM_encours.py
index 4085f65f..d833a94c 100644
--- a/stratus1/src/dpgen/ROM_encours.py
+++ b/stratus1/src/dpgen/ROM_encours.py
@@ -148,30 +148,30 @@ class dpgen_ROM ( Model ) :
 #  
 #   dpgen_ROM_code ( LV_name, nbit, nword, 0, 0, data ) # !!!
 
-  for i in range ( nbit ) :
-    if   i % 4 == 0 :	
-      cellin  = "rom_data_invss"
-      cellmid = "rom_data_midvss"
-      
-      cellout = "rom_data_outvss"
-      
-    elif i % 4 == 1 :
-      cellin  = "rom_data_insel"
-      cellmid = "rom_data_midsel"
-
-      cellout = "rom_data_outsel"
-      
-    elif i % 4 == 2:	
-      cellin  = "rom_data_insel"
-      cellmid = "rom_data_midsel"
-      
-      cellout = "rom_data_outsel"
-
-    elif i % 4 == 3 :	
-      cellin  = "rom_data_invss"
-      cellmid = "rom_data_midvss"
-      
-      cellout = "rom_data_outvss"
+    for i in range ( nbit ) :
+      if   i % 4 == 0 :	
+        cellin  = "rom_data_invss"
+        cellmid = "rom_data_midvss"
+        
+        cellout = "rom_data_outvss"
+        
+      elif i % 4 == 1 :
+        cellin  = "rom_data_insel"
+        cellmid = "rom_data_midsel"
+  
+        cellout = "rom_data_outsel"
+        
+      elif i % 4 == 2:	
+        cellin  = "rom_data_insel"
+        cellmid = "rom_data_midsel"
+        
+        cellout = "rom_data_outsel"
+  
+      elif i % 4 == 3 :	
+        cellin  = "rom_data_invss"
+        cellmid = "rom_data_midvss"
+        
+        cellout = "rom_data_outvss"
     
     instanciate ( cellin
                 , "in%d" % i
diff --git a/stratus1/src/dpgen/dpgen_RF1.py b/stratus1/src/dpgen/dpgen_RF1.py
index d42bf426..32874a41 100644
--- a/stratus1/src/dpgen/dpgen_RF1.py
+++ b/stratus1/src/dpgen/dpgen_RF1.py
@@ -1,4 +1,4 @@
-#!/usr/bin/pythn
+#!/usr/bin/python
 
 # This file is part of the Coriolis Project.
 # Copyright (C) Laboratoire LIP6 - Departement ASIM
diff --git a/stratus1/src/dpgen/dpgen_ROM.py b/stratus1/src/dpgen/dpgen_ROM.py
index 9f300ba6..4b439dc5 100644
--- a/stratus1/src/dpgen/dpgen_ROM.py
+++ b/stratus1/src/dpgen/dpgen_ROM.py
@@ -416,12 +416,12 @@ class TopRom ( Model ) :
                 , 'vdd'   : self.vdd
                 , 'vss'   : self.vss
                 }
-    	if self.nword != 64 : thisMap['col'] = col[j]
-    	else                : thisMap['col'] = One ( 1 )
-    	And23[j] = Inst ( "rom_dec_line23"
-                        , "and23_%d" % j
-                        , map = thisMap
-                        )
+      if self.nword != 64 : thisMap['col'] = col[j]
+      else                : thisMap['col'] = One ( 1 )
+      And23[j] = Inst ( "rom_dec_line23"
+                      , "and23_%d" % j
+                      , map = thisMap
+                      )
         
     if type == 0 : model = "rom_dec_selmux23"
     else         : model = "rom_dec_selmux23_rs"