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Do not generate IEEE VHDL when driving vst files (silly me).

This commit is contained in:
Jean-Paul Chaput 2015-05-21 14:55:38 +02:00
parent b1ca43fd57
commit 20ac9080d6
1 changed files with 4 additions and 1 deletions
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5
crlcore/src/ccore/alliance/vst/VstDriver.cpp
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@ -39,7 +39,10 @@ namespace CRL {
void vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState )
{
NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, Vhdl::Entity::EntityMode|Vhdl::Entity::IeeeMode );
Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell
, Vhdl::Entity::EntityMode
//| Vhdl::Entity::IeeeMode
);
string celltest = cellPath;
ofstream ccelltest ( celltest.c_str() );