From 20ac9080d68356203ac070f977aa8a2fae897d52 Mon Sep 17 00:00:00 2001
From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Thu, 21 May 2015 14:55:38 +0200
Subject: [PATCH] Do not generate IEEE VHDL when driving vst files (silly me).

---
 crlcore/src/ccore/alliance/vst/VstDriver.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/crlcore/src/ccore/alliance/vst/VstDriver.cpp b/crlcore/src/ccore/alliance/vst/VstDriver.cpp
index ceedb0d3..c93da64e 100644
--- a/crlcore/src/ccore/alliance/vst/VstDriver.cpp
+++ b/crlcore/src/ccore/alliance/vst/VstDriver.cpp
@@ -39,7 +39,10 @@ namespace CRL {
   void  vstDriver ( const string cellPath, Cell *cell, unsigned int &saveState )
   {
     NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
-    Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, Vhdl::Entity::EntityMode|Vhdl::Entity::IeeeMode );
+    Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell
+                                                            , Vhdl::Entity::EntityMode
+                                                          //| Vhdl::Entity::IeeeMode
+                                                            );
     string        celltest   = cellPath;
     ofstream      ccelltest  ( celltest.c_str() );