71 lines
3.0 KiB
TeX
71 lines
3.0 KiB
TeX
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\begin{itemize}
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\item Name : DpgenRf1, DpgenRf1r0 -- Register File Macro-Generator
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\item Description : Generates a register file of \verb-regNumber- words of \verb-n- bits without decoder named \verb-modelname-.
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\item How it works :
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\begin{itemize}
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\item datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal.
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\item when sel is set to zero datain0 is used to write the register word, otherwise it will be datain1
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\item selr, selw : this register file have no decoder, so selr have a bus width equal to \verb-regNumber-. One bit for each word
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\item The DpgenRf1r0 variant differs from the DpgenRf1 in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero
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\end{itemize}
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\item Terminal Names :
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\begin{itemize}
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\item ckok : clock signal (input, 1 bit)
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\item sel : select the write bus (input, 1 bit)
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\item selr : the decoded read address (input, \verb-regNumber- bits)
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\item selw : the decoded write address (input, \verb-regNumber- bits)
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\item datain0 : first write bus (input, \verb-n- bits)
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\item datain1 : second write bus (input, \verb-n- bits)
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\item dataout : read bus (output, \verb-n- bits)
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\item vdd : power
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\item vss : ground
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\end{itemize}
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\item Parameters : Parameters are given with a map called \verb-param-.
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\begin{itemize}
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\item nbit : Defines the size of the words (even, between 2 and 64)
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\item nword : Defines the number of the words (even, between 4 and 32)
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\end{itemize}
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% \item Behavior :
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%\begin{verbatim}
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%\end{verbatim}
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\item Example :
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\begin{verbatim}
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class myClass ( Model ) :
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def Interface ( self ) :
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self.nbit = self._param['nbit']
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self.nword = self._param['nword']
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self._ck = LogicIn ( "ck", 1 )
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self._sel = LogicIn ( "sel", 1 )
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self._selr = LogicIn ( "selr", self.nword )
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self._selw = LogicIn ( "selw", self.nword )
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self._datain0 = LogicIn ( "datain0", self.nbit )
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self._datain1 = LogicIn ( "datain1", self.nbit )
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self._dataout = LogicOut ( "dataout", self.nbit )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Inst ( 'DpgenRf1'
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, param = { 'nword' : self.nword
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, 'nbit' : self.nbit
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}
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, map = { 'ck' : self._ck
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, 'sel' : self._sel
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, 'selr' : self._selr
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, 'selw' : self._selw
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, 'datain0' : self._datain0
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, 'datain1' : self._datain1
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, 'dataout' : self._dataout
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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\end{verbatim}
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\end{itemize}
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