87 lines
3.3 KiB
XML
87 lines
3.3 KiB
XML
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<?xml version="1.0" encoding="UTF-8"?>
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<circuit name="design" techno="myTech">
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<parameters>
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<parameter name="temp" value="27.0"/>
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<parameter name="Vdd" value="1.2"/>
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<parameter name="Vss" value="0.0"/>
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<parameter name="L" value="0.10e-6"/>
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<parameter name="Ids" value="30e-6"/>
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<parameter name="Veg" value="0.12"/>
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<parameterEq name="complex" equation="myEq"/>
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</parameters>
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<netlist>
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<instances>
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<instance name="nmos1" model="Transistor" mostype="NMOS" sourceBulkConnected="True">
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<connectors>
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<connector name="G"/>
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<connector name="D"/>
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<connector name="S"/>
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</connectors>
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<transistors>
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<transistor name="m1">
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<connection gate="G" source="S" drain="D" bulk="S"/>
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</transistor>
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</transistors>
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</instance>
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<instance name="pmos1" model="Transistor" mostype="PMOS" sourceBulkConnected="True">
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<connectors>
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<connector name="G"/>
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<connector name="D"/>
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<connector name="S"/>
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</connectors>
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<transistors>
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<transistor name="m1">
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<connection gate="G" source="S" drain="D" bulk="S"/>
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</transistor>
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</transistors>
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</instance>
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</instances>
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<nets>
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<net name="vdd" type="power" isExternal="True">
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<connector instance="pmos1" name="S"/>
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</net>
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<net name="vss" type="ground" isExternal="True">
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<connector instance="nmos1" name="S"/>
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</net>
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<net name="in" type="logical" isExternal="True">
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<connector instance="nmos1" name="G"/>
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<connector instance="pmos1" name="G"/>
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</net>
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<net name="out" type="logical" isExternal="True">
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<connector instance="nmos1" name="D"/>
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<connector instance="pmos1" name="D"/>
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</net>
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</nets>
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</netlist>
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<schematic zoom="1.0">
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<instance name="nmos1" x="2490" y="2600" sym="ID"/>
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<instance name="pmos1" x="2490" y="2300" sym="ID"/>
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</schematic>
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<sizing>
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<instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3" callOrder="0">
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<constraint param="Temp" ref="design" refParam="temp"/>
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<constraint param="Ids" ref="design" refParam="Ids"/>
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<constraint param="L" ref="design" refParam="L"/>
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<constraint param="Veg" ref="design" refParam="Veg"/>
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<constraint param="Vd" ref="design" refParam="Vdd" factor="0.5"/>
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<constraint param="Vs" ref="design" refParam="Vdd"/>
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</instance>
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<instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3" callOrder="1">
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<constraint param="Temp" ref="design" refParam="temp"/>
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<constraint param="Ids" ref="design" refParam="Ids"/>
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<constraint param="L" ref="design" refParam="L"/>
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<constraint param="Vs" ref="design" refParam="Vdd"/>
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<constraint param="Vg" ref="pmos1" refParam="Vg"/>
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<constraint param="Vd" ref="pmos1" refParam="Vd"/>
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<constraint param="another" refEquation="myEq" factor="-2.5"/>
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</instance>
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<equations>
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<eq name="myEq" equation="A/more+complex*equation"/>
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</equations>
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</sizing>
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<layout>
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<instance name="pmos1" style="Common transistor"/>
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<instance name="nmos1" style="Rotate transistor"/>
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</layout>
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</circuit>
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