Adding code examples for openChams parser/driver in c++/python.
This commit is contained in:
Damien Dupuis
parent
76820567a7
commit
73d8035ad8
|
|
@ -1,3 +1,4 @@
|
|||
ADD_SUBDIRECTORY(cif)
|
||||
ADD_SUBDIRECTORY(agds)
|
||||
ADD_SUBDIRECTORY(dtr)
|
||||
ADD_SUBDIRECTORY(openChams)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
ADD_SUBDIRECTORY(cplusplus)
|
||||
ADD_SUBDIRECTORY(python)
|
||||
|
||||
INSTALL ( FILES inverter.xml DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
INCLUDE_DIRECTORIES ( ${VLSISAPD_SOURCE_DIR}/src/openChams/src ${LIBXML2_INCLUDE_DIR})
|
||||
ADD_EXECUTABLE ( driveOpenChams driveOpenChams.cpp )
|
||||
ADD_EXECUTABLE ( parseOpenChams parseOpenChams.cpp )
|
||||
TARGET_LINK_LIBRARIES ( driveOpenChams openChams ${LIBXML_LIBRARIES}) # 'driveOpenChams' is the name of the executable and 'openChams' the name of the target library in openChams/src/CMakeLists.txt
|
||||
TARGET_LINK_LIBRARIES ( parseOpenChams openChams ${LIBXML_LIBRARIES})
|
||||
INSTALL ( TARGETS driveOpenChams parseOpenChams DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
|
||||
INSTALL ( FILES driveOpenChams.cpp parseOpenChams.cpp DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
|
||||
INSTALL ( FILES cmake.ex DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams RENAME CMakeLists.txt )
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
PROJECT(PARSEDRIVEOPENCHAMS)
|
||||
|
||||
CMAKE_MINIMUM_REQUIRED(VERSION 2.4.0)
|
||||
|
||||
SET(CMAKE_MODULE_PATH "$ENV{VLSISAPD_USER_TOP}/share/cmake/Modules"
|
||||
"$ENV{VLSISAPD_TOP}/share/cmake/Modules"
|
||||
)
|
||||
|
||||
FIND_PACKAGE(VLSISAPD REQUIRED)
|
||||
FIND_PACKAGE(Libxml2 REQUIRED)
|
||||
|
||||
IF(OPENCHAMS_FOUND)
|
||||
INCLUDE_DIRECTORIES(${OPENCHAMS_INCLUDE_DIR} ${LIBXML2_INCLUDE_DIR})
|
||||
ADD_EXECUTABLE(driveOpenChams driveOpenChams.cpp)
|
||||
ADD_EXECUTABLE(parseOpenChams parseOpenChams.cpp)
|
||||
TARGET_LINK_LIBRARIES(driveOpenChams ${OPENCHAMS_LIBRARY} ${LIBXML2_LIBRARIES})
|
||||
TARGET_LINK_LIBRARIES(parseOpenChams ${OPENCHAMS_LIBRARY} ${LIBXML2_LIBRARIES})
|
||||
ENDIF(OPENCHAMS_FOUND)
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
#include <string>
|
||||
using namespace std;
|
||||
|
||||
#include "vlsisapd/openChams/Circuit.h"
|
||||
#include "vlsisapd/openChams/Netlist.h"
|
||||
#include "vlsisapd/openChams/Instance.h"
|
||||
#include "vlsisapd/openChams/Transistor.h"
|
||||
#include "vlsisapd/openChams/Net.h"
|
||||
#include "vlsisapd/openChams/Schematic.h"
|
||||
#include "vlsisapd/openChams/Sizing.h"
|
||||
#include "vlsisapd/openChams/Operator.h"
|
||||
#include "vlsisapd/openChams/Layout.h"
|
||||
|
||||
int main(int argc, char * argv[]) {
|
||||
OpenChams::Circuit* circuit = new OpenChams::Circuit(OpenChams::Name("design"), OpenChams::Name("myTech"));
|
||||
// value parameters
|
||||
circuit->addParameter(OpenChams::Name("temp"), 27.0 );
|
||||
circuit->addParameter(OpenChams::Name("Vdd") , 1.2 );
|
||||
circuit->addParameter(OpenChams::Name("Vss") , 0.0 );
|
||||
circuit->addParameter(OpenChams::Name("L") , 0.1e-6);
|
||||
circuit->addParameter(OpenChams::Name("Ids") , 30e-6 );
|
||||
circuit->addParameter(OpenChams::Name("Veg") , 0.12 );
|
||||
// equation parameters
|
||||
circuit->addParameter(OpenChams::Name("complex"), "myEq");
|
||||
|
||||
// netlist
|
||||
OpenChams::Netlist* netlist = circuit->createNetlist();
|
||||
// instances
|
||||
// nmos1
|
||||
OpenChams::Instance* inst_nmos1 = netlist->addInstance(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), OpenChams::Name("NMOS"), true);
|
||||
inst_nmos1->addConnector(OpenChams::Name("G"));
|
||||
inst_nmos1->addConnector(OpenChams::Name("S"));
|
||||
inst_nmos1->addConnector(OpenChams::Name("D"));
|
||||
OpenChams::Transistor* tr_nmos1 = inst_nmos1->addTransistor(OpenChams::Name("m1"));
|
||||
tr_nmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_nmos1
|
||||
tr_nmos1->setSource(OpenChams::Name("S"));
|
||||
tr_nmos1->setDrain (OpenChams::Name("D"));
|
||||
tr_nmos1->setBulk (OpenChams::Name("S"));
|
||||
// pmos1
|
||||
OpenChams::Instance* inst_pmos1 = netlist->addInstance(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), OpenChams::Name("PMOS"), true);
|
||||
inst_pmos1->addConnector(OpenChams::Name("G"));
|
||||
inst_pmos1->addConnector(OpenChams::Name("S"));
|
||||
inst_pmos1->addConnector(OpenChams::Name("D"));
|
||||
OpenChams::Transistor* tr_pmos1 = inst_pmos1->addTransistor(OpenChams::Name("m1"));
|
||||
tr_pmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_pmos1
|
||||
tr_pmos1->setSource(OpenChams::Name("S"));
|
||||
tr_pmos1->setDrain (OpenChams::Name("D"));
|
||||
tr_pmos1->setBulk (OpenChams::Name("S"));
|
||||
// nets
|
||||
OpenChams::Net* _vdd = netlist->addNet(OpenChams::Name("vdd"), OpenChams::Name("power") , true);
|
||||
OpenChams::Net* _vss = netlist->addNet(OpenChams::Name("vss"), OpenChams::Name("ground") , true);
|
||||
OpenChams::Net* _in = netlist->addNet(OpenChams::Name("in" ), OpenChams::Name("logical"), true);
|
||||
OpenChams::Net* _out = netlist->addNet(OpenChams::Name("out"), OpenChams::Name("logical"), true);
|
||||
_vdd->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("S"));
|
||||
_vss->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("S"));
|
||||
_in->connectTo (OpenChams::Name("nmos1"), OpenChams::Name("G"));
|
||||
_in->connectTo (OpenChams::Name("pmos1"), OpenChams::Name("G"));
|
||||
_out->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("D"));
|
||||
_out->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("D"));
|
||||
|
||||
// schematic
|
||||
OpenChams::Schematic* schematic = circuit->createSchematic(1.0);
|
||||
schematic->addInstance(OpenChams::Name("nmos1"), 2490, 2600, OpenChams::Name("ID"));
|
||||
schematic->addInstance(OpenChams::Name("pmos1"), 2490, 2300, OpenChams::Name("ID"));
|
||||
// sizing
|
||||
OpenChams::Sizing* sizing = circuit->createSizing();
|
||||
OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"), 0);
|
||||
op_pmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
|
||||
op_pmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids") );
|
||||
op_pmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L") );
|
||||
op_pmos1->addConstraint(OpenChams::Name("Veg") , OpenChams::Name("design"), OpenChams::Name("Veg") );
|
||||
op_pmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("design"), OpenChams::Name("Vdd") , 0.5);
|
||||
op_pmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd") );
|
||||
OpenChams::Operator* op_nmos1 = sizing->addOperator(OpenChams::Name("nmos1"), OpenChams::Name("OPW(Vg,Vs)"), OpenChams::Name("BSIM3V3"), 1);
|
||||
op_nmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
|
||||
op_nmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids" ));
|
||||
op_nmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L" ));
|
||||
op_nmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd" ));
|
||||
op_nmos1->addConstraint(OpenChams::Name("Vg") , OpenChams::Name("pmos1") , OpenChams::Name("Vg" ));
|
||||
op_nmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("pmos1") , OpenChams::Name("Vd" ));
|
||||
op_nmos1->addConstraint(OpenChams::Name("another"), OpenChams::Name("myEq"), -2.5 );
|
||||
// layout
|
||||
OpenChams::Layout* layout = circuit->createLayout();
|
||||
layout->addInstance(OpenChams::Name("pmos1"), OpenChams::Name("Common transistor"));
|
||||
layout->addInstance(OpenChams::Name("nmos1"), OpenChams::Name("Rotate transistor"));
|
||||
|
||||
circuit->writeToFile("./myInverter.xml");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
#include <iostream>
|
||||
#include <string>
|
||||
#include <map>
|
||||
#include <vector>
|
||||
using namespace std;
|
||||
|
||||
#include "vlsisapd/openChams/Circuit.h"
|
||||
#include "vlsisapd/openChams/Name.h"
|
||||
#include "vlsisapd/openChams/Parameters.h"
|
||||
#include "vlsisapd/openChams/Netlist.h"
|
||||
#include "vlsisapd/openChams/Instance.h"
|
||||
#include "vlsisapd/openChams/Net.h"
|
||||
#include "vlsisapd/openChams/Transistor.h"
|
||||
#include "vlsisapd/openChams/Schematic.h"
|
||||
#include "vlsisapd/openChams/Sizing.h"
|
||||
#include "vlsisapd/openChams/Operator.h"
|
||||
#include "vlsisapd/openChams/Layout.h"
|
||||
|
||||
int main(int argc, char * argv[]) {
|
||||
OpenChams::Circuit* circuit = OpenChams::Circuit::readFromFile("./inverter.xml");
|
||||
|
||||
cerr << circuit->getName().getString() << endl;
|
||||
cerr << " + parameters" << endl;
|
||||
OpenChams::Parameters params = circuit->getParameters();
|
||||
if (!params.isEmpty()) {
|
||||
for (map<OpenChams::Name, double>::const_iterator it = params.getValues().begin() ; it != params.getValues().end() ; ++it) {
|
||||
cerr << " | | " << ((*it).first).getString() << " : " << (*it).second << endl;
|
||||
}
|
||||
for (map<OpenChams::Name, string>::const_iterator it = params.getEqValues().begin() ; it != params.getEqValues().end() ; ++it) {
|
||||
cerr << " | | " << ((*it).first).getString() << " : " << (*it).second << endl;
|
||||
}
|
||||
}
|
||||
cerr << " + netlist" << endl;
|
||||
cerr << " | + instances" << endl;
|
||||
OpenChams::Netlist* netlist = circuit->getNetlist();
|
||||
if (netlist && !netlist->hasNoInstances()) {
|
||||
for (size_t i = 0 ; i < netlist->getInstances().size() ; i++) {
|
||||
OpenChams::Instance* inst = netlist->getInstances()[i];
|
||||
cerr << " | | + " << inst->getName().getString() << " : " << inst->getModel().getString() << " - " << inst->getMosType().getString() << " - " << (inst->isSourceBulkConnected()?"true":"false") << endl;
|
||||
cerr << " | | | + connectors" << endl;
|
||||
for (map<OpenChams::Name, OpenChams::Net*>::const_iterator cit = inst->getConnectors().begin() ; cit != inst->getConnectors().end() ; ++cit) {
|
||||
cerr << " | | | | " << ((*cit).first).getString() << " : " << ((*cit).second)->getName().getString() << endl;
|
||||
}
|
||||
cerr << " | | | + transistors" << endl;
|
||||
for (size_t j = 0 ; j < inst->getTransistors().size() ; j++) {
|
||||
OpenChams::Transistor* tr = inst->getTransistors()[j];
|
||||
cerr << " | | | | name: " << tr->getName().getString() << " - gate: " << tr->getGate().getString() << " - source: " << tr->getSource().getString() << " - drain: " << tr->getDrain().getString() << " - bulk: " << tr->getBulk().getString() << endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
cerr << " | + nets" << endl;
|
||||
if (!netlist->hasNoNets()) {
|
||||
for (size_t i = 0 ; i < netlist->getNets().size() ; i++) {
|
||||
OpenChams::Net* net = netlist->getNets()[i];
|
||||
cerr << " | | + " << net->getName().getString() << " : " << net->getType().getString() << " - " << (net->isExternal()?"true":"false") << endl;
|
||||
cerr << " | | | + connections" << endl;
|
||||
for (size_t j = 0 ; j < net->getConnections().size() ; j++) {
|
||||
OpenChams::Net::Connection* connect = net->getConnections()[j];
|
||||
cerr << " | | | | " << connect->getInstanceName().getString() << "." << connect->getConnectorName().getString() << endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
OpenChams::Schematic* schematic = circuit->getSchematic();
|
||||
if (schematic && !schematic->hasNoInstances()) {
|
||||
cerr << " + schematic - zoom: " << schematic->getZoom() << endl;
|
||||
for (map<OpenChams::Name, OpenChams::Schematic::Infos*>::const_iterator sit = schematic->getInstances().begin() ; sit != schematic->getInstances().end() ; ++sit) {
|
||||
OpenChams::Schematic::Infos* inf = (*sit).second;
|
||||
cerr << " | name: " << ((*sit).first).getString() << " - x: " << inf->getX() << " - y: " << inf->getY() << " - symmetry: " << inf->getSymmetry().getString() << endl;
|
||||
}
|
||||
}
|
||||
OpenChams::Sizing* sizing = circuit->getSizing();
|
||||
if (sizing) {
|
||||
cerr << " + sizing" << endl;
|
||||
if (!sizing->hasNoOperators()) {
|
||||
for (map<OpenChams::Name, OpenChams::Operator*>::const_iterator oit = sizing->getOperators().begin() ; oit != sizing->getOperators().end() ; ++oit) {
|
||||
OpenChams::Operator* op = (*oit).second;
|
||||
cerr << " | + instance name: " << ((*oit).first).getString() << " - operator: " << op->getName().getString() << " - simulModel: " << op->getSimulModel().getString() << " - callOrder: " << op->getCallOrder() << endl;
|
||||
if (!op->hasNoConstraints()) {
|
||||
for (map<OpenChams::Name, OpenChams::Operator::Constraint*>::const_iterator cit = op->getConstraints().begin() ; cit != op->getConstraints().end() ; ++cit) {
|
||||
OpenChams::Operator::Constraint* cstr = (*cit).second;
|
||||
cerr << " | | + param: " << ((*cit).first).getString() << " - ref: " << cstr->getRef().getString() << " - refParam: " << cstr->getRefParam().getString() << " - factor: " << cstr->getFactor() << endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (!sizing->hasNoEquations()) {
|
||||
cerr << " | + equations" << endl;
|
||||
for (map<OpenChams::Name, string>::const_iterator eit = sizing->getEquations().begin() ; eit != sizing->getEquations().end() ; ++eit) {
|
||||
cerr << " | | " << ((*eit).first).getString() << " : " << (*eit).second << endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
OpenChams::Layout* layout = circuit->getLayout();
|
||||
if (layout && !layout->hasNoInstance()) {
|
||||
cerr << " + layout" << endl;
|
||||
for (map<OpenChams::Name, OpenChams::Name>::const_iterator lit = layout->getInstances().begin() ; lit != layout->getInstances().end() ; ++lit) {
|
||||
cerr << " | | instance name: " << ((*lit).first).getString() << " - style: " << ((*lit).second).getString() << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<circuit name="design" techno="myTech">
|
||||
<parameters>
|
||||
<parameter name="temp" value="27.0"/>
|
||||
<parameter name="Vdd" value="1.2"/>
|
||||
<parameter name="Vss" value="0.0"/>
|
||||
<parameter name="L" value="0.10e-6"/>
|
||||
<parameter name="Ids" value="30e-6"/>
|
||||
<parameter name="Veg" value="0.12"/>
|
||||
<parameterEq name="complex" equation="myEq"/>
|
||||
</parameters>
|
||||
<netlist>
|
||||
<instances>
|
||||
<instance name="nmos1" model="Transistor" mostype="NMOS" sourceBulkConnected="True">
|
||||
<connectors>
|
||||
<connector name="G"/>
|
||||
<connector name="D"/>
|
||||
<connector name="S"/>
|
||||
</connectors>
|
||||
<transistors>
|
||||
<transistor name="m1">
|
||||
<connection gate="G" source="S" drain="D" bulk="S"/>
|
||||
</transistor>
|
||||
</transistors>
|
||||
</instance>
|
||||
<instance name="pmos1" model="Transistor" mostype="PMOS" sourceBulkConnected="True">
|
||||
<connectors>
|
||||
<connector name="G"/>
|
||||
<connector name="D"/>
|
||||
<connector name="S"/>
|
||||
</connectors>
|
||||
<transistors>
|
||||
<transistor name="m1">
|
||||
<connection gate="G" source="S" drain="D" bulk="S"/>
|
||||
</transistor>
|
||||
</transistors>
|
||||
</instance>
|
||||
</instances>
|
||||
<nets>
|
||||
<net name="vdd" type="power" isExternal="True">
|
||||
<connector instance="pmos1" name="S"/>
|
||||
</net>
|
||||
<net name="vss" type="ground" isExternal="True">
|
||||
<connector instance="nmos1" name="S"/>
|
||||
</net>
|
||||
<net name="in" type="logical" isExternal="True">
|
||||
<connector instance="nmos1" name="G"/>
|
||||
<connector instance="pmos1" name="G"/>
|
||||
</net>
|
||||
<net name="out" type="logical" isExternal="True">
|
||||
<connector instance="nmos1" name="D"/>
|
||||
<connector instance="pmos1" name="D"/>
|
||||
</net>
|
||||
</nets>
|
||||
</netlist>
|
||||
<schematic zoom="1.0">
|
||||
<instance name="nmos1" x="2490" y="2600" sym="ID"/>
|
||||
<instance name="pmos1" x="2490" y="2300" sym="ID"/>
|
||||
</schematic>
|
||||
<sizing>
|
||||
<instance name="pmos1" operator="OPVG(Veg)" simulModel="BSIM3V3" callOrder="0">
|
||||
<constraint param="Temp" ref="design" refParam="temp"/>
|
||||
<constraint param="Ids" ref="design" refParam="Ids"/>
|
||||
<constraint param="L" ref="design" refParam="L"/>
|
||||
<constraint param="Veg" ref="design" refParam="Veg"/>
|
||||
<constraint param="Vd" ref="design" refParam="Vdd" factor="0.5"/>
|
||||
<constraint param="Vs" ref="design" refParam="Vdd"/>
|
||||
</instance>
|
||||
<instance name="nmos1" operator="OPW(Vg,Vs)" simulModel="BSIM3V3" callOrder="1">
|
||||
<constraint param="Temp" ref="design" refParam="temp"/>
|
||||
<constraint param="Ids" ref="design" refParam="Ids"/>
|
||||
<constraint param="L" ref="design" refParam="L"/>
|
||||
<constraint param="Vs" ref="design" refParam="Vdd"/>
|
||||
<constraint param="Vg" ref="pmos1" refParam="Vg"/>
|
||||
<constraint param="Vd" ref="pmos1" refParam="Vd"/>
|
||||
<constraint param="another" refEquation="myEq" factor="-2.5"/>
|
||||
</instance>
|
||||
<equations>
|
||||
<eq name="myEq" equation="A/more+complex*equation"/>
|
||||
</equations>
|
||||
</sizing>
|
||||
<layout>
|
||||
<instance name="pmos1" style="Common transistor"/>
|
||||
<instance name="nmos1" style="Rotate transistor"/>
|
||||
</layout>
|
||||
</circuit>
|
||||
|
|
@ -0,0 +1 @@
|
|||
INSTALL ( FILES driveOpenChams.py parseOpenChams.py DESTINATION share/doc/coriolis2/examples/vlsisapd/openChams )
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
from OPENCHAMS import *
|
||||
|
||||
circuit = Circuit(Name("design"), Name("myTech"))
|
||||
# value parameters
|
||||
circuit.addParameter(Name("temp"), 27.0 )
|
||||
circuit.addParameter(Name("Vdd") , 1.2 )
|
||||
circuit.addParameter(Name("Vss") , 0.0 )
|
||||
circuit.addParameter(Name("L") , 0.1e-6)
|
||||
circuit.addParameter(Name("Ids") , 30e-6 )
|
||||
circuit.addParameter(Name("Veg") , 0.12 )
|
||||
# equation parameters
|
||||
circuit.addParameter(Name("complex"), "myEq")
|
||||
|
||||
# netlist :
|
||||
netlist = circuit.createNetlist()
|
||||
# instances
|
||||
# nmos1
|
||||
inst_nmos1 = netlist.addInstance("nmos1", "Transistor", "NMOS", True)
|
||||
inst_nmos1.addConnector("G")
|
||||
inst_nmos1.addConnector("S")
|
||||
inst_nmos1.addConnector("D")
|
||||
tr_nmos1 = inst_nmos1.addTransistor("m1")
|
||||
tr_nmos1.gate = "G" # the name of the connector of inst_nmos1
|
||||
tr_nmos1.source = "S"
|
||||
tr_nmos1.drain = "D"
|
||||
tr_nmos1.bulk = "S"
|
||||
# pmos1
|
||||
inst_pmos1 = netlist.addInstance("pmos1", "Transistor", "PMOS", True)
|
||||
inst_pmos1.addConnector("G")
|
||||
inst_pmos1.addConnector("S")
|
||||
inst_pmos1.addConnector("D")
|
||||
tr_pmos1 = inst_pmos1.addTransistor("m1")
|
||||
tr_pmos1.gate = "G" # the name of the connector of inst_pmos1
|
||||
tr_pmos1.source = "S"
|
||||
tr_pmos1.drain = "D"
|
||||
tr_pmos1.bulk = "S"
|
||||
# nets
|
||||
_vdd = netlist.addNet("vdd", "power" , True)
|
||||
_vss = netlist.addNet("vss", "ground" , True)
|
||||
_in = netlist.addNet("in" , "logical", True)
|
||||
_out = netlist.addNet("out", "logical", True)
|
||||
_vdd.connectTo("pmos1", "S")
|
||||
_vss.connectTo("nmos1", "S")
|
||||
_in.connectTo ("nmos1", "G")
|
||||
_in.connectTo ("pmos1", "G")
|
||||
_out.connectTo("nmos1", "D")
|
||||
_out.connectTo("pmos1", "D")
|
||||
# schematic
|
||||
schematic = circuit.createSchematic(1.0)
|
||||
schematic.addInstance("nmos1", 2490, 2600, "ID")
|
||||
schematic.addInstance("pmos1", 2490, 2300, "ID")
|
||||
# sizing
|
||||
sizing = circuit.createSizing()
|
||||
op_pmos1 = sizing.addOperator("pmos1", "OPVG(Veg)" , "BSIM3V3", 0)
|
||||
op_pmos1.addConstraint("Temp", "design", "temp")
|
||||
op_pmos1.addConstraint("Ids" , "design", "Ids" )
|
||||
op_pmos1.addConstraint("L" , "design", "L" )
|
||||
op_pmos1.addConstraint("Veg" , "design", "Veg" )
|
||||
op_pmos1.addConstraint("Vd" , "design", "Vdd", 0.5)
|
||||
op_pmos1.addConstraint("Vs" , "design", "Vdd" )
|
||||
op_nmos1 = sizing.addOperator("nmos1", "OPW(Vg,Vs)", "BSIM3V3", 1)
|
||||
op_nmos1.addConstraint("Temp", "design", "temp")
|
||||
op_nmos1.addConstraint("Ids" , "design", "Ids" )
|
||||
op_nmos1.addConstraint("L" , "design", "L" )
|
||||
op_nmos1.addConstraint("Vs" , "design", "Vdd" )
|
||||
op_nmos1.addConstraint("Vg" , "pmos1" , "Vg" )
|
||||
op_nmos1.addConstraint("Vd" , "pmos1" , "Vd" )
|
||||
op_nmos1.addConstraint("another", "myEq", -2.5 )
|
||||
# layout
|
||||
layout = circuit.createLayout()
|
||||
layout.addInstance("pmos1", "Common transistor")
|
||||
layout.addInstance("nmos1", "Rotate transistor")
|
||||
|
||||
circuit.writeToFile("./myInverter.xml")
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
from OPENCHAMS import *
|
||||
|
||||
circuit = Circuit.readFromFile("./inverter.xml")
|
||||
|
||||
print circuit.name
|
||||
# circuit parameters
|
||||
print " + parameters"
|
||||
for param in circuit.parameters.getValues():
|
||||
print " | |", param.key, ":", param.value
|
||||
for param in circuit.parameters.getEqValues():
|
||||
print " | |", param.key, ":", param.value
|
||||
# netlist
|
||||
print " + netlist"
|
||||
# instances
|
||||
print " | + instances"
|
||||
for instance in circuit.netlist.getInstances():
|
||||
print " | | +", instance.name, ":", instance.model, instance.mosType, instance.sourceBulkConnected
|
||||
print " | | | + connectors"
|
||||
for conn in instance.getConnectors():
|
||||
print " | | | |", conn.key, ":", conn.value.name
|
||||
print " | | | + transistors"
|
||||
for tr in instance.getTransistors():
|
||||
print " | | | | name:", tr.name, "- gate:", tr.gate, "- source:", tr.source, "- drain:", tr.drain, "- bulk:", tr.bulk
|
||||
# nets
|
||||
print " | + nets"
|
||||
for net in circuit.netlist.getNets():
|
||||
print " | | +", net.name, ":", net.type, net.external
|
||||
print " | | | + connections"
|
||||
for conn in net.getConnections():
|
||||
print " | | | | %s.%s"%(conn.instanceName, conn.connectorName)
|
||||
# schematic
|
||||
print " + schematic - zoom:", circuit.schematic.zoom
|
||||
for instance in circuit.schematic.getInstances():
|
||||
print " | name:", instance.key, "- x:", instance.value.x, "- y:", instance.value.y, "- symmetry:", instance.value.symmetry
|
||||
# sizing
|
||||
print " + sizing"
|
||||
for op in circuit.sizing.getOperators():
|
||||
print " | + instance name:", op.key, "- operator:", op.value.name, "- simulModel:", op.value.simulModel, "- callOrder:", op.value.callOrder
|
||||
for constraint in op.value.getConstraints():
|
||||
print " | | + param:", constraint.key, "- ref:", constraint.value.ref, "- refParam:", constraint.value.refParam, "- factor:", constraint.value.factor
|
||||
print " | + equations"
|
||||
for eq in circuit.sizing.getEquations():
|
||||
print " | |", eq.key, ":", eq.value
|
||||
# layout
|
||||
print " + layout"
|
||||
for inst in circuit.layout.getInstances():
|
||||
print " | | instance name:", inst.key, "- style:", inst.value
|
||||
|
||||
Loading…
Reference in New Issue