2010-07-12 10:33:22 -05:00
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#!/usr/bin/python
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#
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2012-12-03 02:31:26 -06:00
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# This file is part of the Coriolis Software.
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2016-01-20 17:41:19 -06:00
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# Copyright (c) UPMC 2008-2016, All Rights Reserved
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2010-07-12 10:33:22 -05:00
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#
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2012-12-03 02:31:26 -06:00
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# +-----------------------------------------------------------------+
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2010-07-12 10:33:22 -05:00
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# | C O R I O L I S |
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2012-12-03 02:31:26 -06:00
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# | S t r a t u s - Netlists/Layouts Description |
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2010-07-12 10:33:22 -05:00
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./stratus.py" |
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2012-12-03 02:31:26 -06:00
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# +-----------------------------------------------------------------+
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2010-07-12 10:33:22 -05:00
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2012-12-03 02:31:26 -06:00
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try:
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import sys
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Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
2015-02-25 15:17:44 -06:00
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import traceback
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2012-12-03 02:31:26 -06:00
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import Cfg
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import CRL
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2010-07-12 10:33:22 -05:00
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2012-12-03 02:31:26 -06:00
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# Triggers the default configuration files loading.
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CRL.AllianceFramework.get()
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2012-03-09 01:49:45 -06:00
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2012-12-03 02:31:26 -06:00
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Cfg.Configuration.pushDefaultPriority(Cfg.Parameter.Priority.ApplicationBuiltin)
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Cfg.getParamString('stratus1.format' ).setString('vst')
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Cfg.getParamString('stratus1.simulator').setString('asimut')
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Cfg.Configuration.popDefaultPriority()
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2012-03-09 01:49:45 -06:00
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2012-12-03 02:31:26 -06:00
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print ' o Stratus Configuration:'
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print ' - Netlist format: <%s>.' % Cfg.getParamString('stratus1.format').asString()
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print ' - Simulator: <%s>.' % Cfg.getParamString('stratus1.simulator').asString()
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from st_model import *
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from st_net import *
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from st_instance import *
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from st_placement import *
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2015-03-17 16:50:00 -05:00
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#from st_placeAndRoute import *
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2012-12-03 02:31:26 -06:00
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from st_ref import *
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from st_generate import *
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from st_const import *
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from st_cat import *
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from st_param import *
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from st_getrealmodel import GetWeightTime, GetWeightArea, GetWeightPower
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from util_Const import *
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from util_Defs import *
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from util_Misc import *
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from util_Gen import *
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from util_Shift import *
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from util_uRom import *
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from util import *
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from patterns import *
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except ImportError, e:
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module = str(e).split()[-1]
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2012-03-09 01:49:45 -06:00
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2012-12-03 02:31:26 -06:00
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print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module
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print ' Please check the integrity of the <coriolis> package.'
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sys.exit(1)
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except Exception, e:
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print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python'
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print ' modules. Something may be wrong at Python/C API level.\n'
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print ' %s' % e
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sys.exit(2)
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Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
2015-02-25 15:17:44 -06:00
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DoNetlist = 0x0001
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DoLayout = 0x0002
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DoStop = 0x0004
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def buildModel ( name, flags ):
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try:
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Added support for "same layer" dogleg. Big fix for pad routing.
* Change: In Knik, in Vertex, add a "blocked" flag to signal disabled
vertexes in the grid (must not be used by the global router).
Modificate the Graph::getVertex() method so that when a vertex
is geometrically queried, if is a blocked one, return a non-blocked
neighbor. This mechanism is introduced to, at last, prevent the
global router to go *under* the pad in case of a commplete chip.
* New: In Katabatic, in AutoSegment, a new state has been added: "reduced".
A reduced segment is in the same layer as it's perpandiculars.
To be reduced, a segments has to be connected on source & target to
AutoContactTurn, both of the perpandiculars must be of the same layer
(below or above) and it's length must not exceed one pitch in the
perpandicular direction.
To reduce an AutoSegment, call ::reduce() and to revert the state,
call ::raise(). Two associated predicates are associated:
::canReduce() and ::mustRaise().
Note: No two adjacent segments can be reduced at the same time.
* Bug: In Katabatic, in GCellTopology, add a new method ::doRp_AccessPad()
to connect to the pads. Create wiring, fixed and non managed by
Katabatic, to connect the pad connector layer to the lowest routing
layers (depth 1 & 2). The former implementation was sometimes leading
to gaps (sheared contact) that *must not* occurs during the building
stage.
Remark: This bug did put under the light the fact that the initial
wiring must be created without gaps. Gaps are closed by making doglegs
on contacts. But this mechanism could only work when the database if
fully initialised (the cache is up to date). Otherwise various problems
arise, in the canonization process for example.
* New: In Katabatic, in AutoContactTerminal::getNativeConstraintBox(),
when anchored on a RoutingPad, now take account the potential rotation
of the Path's transformation. Here again, for the chip's pads.
* New: In Kite, support for reduced AutoSegment. TrackSegment associateds
to reduced AutoSegment are *not* inserted into track to become
effectively invisibles. When a segment becomes reduced, a TrackEvent
is generated to remove it. Conversely when it is raised a RoutingEvent
is created/rescheduled to insert it. All this is mostly managed inside
the Session::revalidate() method.
* New: In Kite, in KiteEngine::createGlobalGraph(), in case of a chip,
mark all global routing vertexes (Knik) that are under a pad, as blockeds.
* Bug: In Cumulus, in PadsCorona.Side.getAxis(), inversion between X and
Y coordinate of the chip size. Did not show until a non-square chip
was routed (i.e. our MIPS R3000).
* Change: In Stratus1, in st_placement.py add the ClockBuffer class for
backward compatibility with the MIPS32 bench. Have to review this
functionnality coming from the deprecated placeAndroute.py.
In st_instance.py, no longer creates the Plug ring of a Net.
In my opinion it just clutter the display until the P&R is called.
Can re-enable later as an option (in Unicorn).
* Change: In Unicorn, in cgt.py, more reliable way of loading then running
user supplied scripts. Borrowed from alliance-checker-toolkit doChip.py .
2015-08-16 16:29:28 -05:00
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#print name
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Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
2015-02-25 15:17:44 -06:00
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module = __import__( name, globals(), locals(), name )
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if not module.__dict__.has_key(name):
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print '[ERROR] Stratus module <%s> do not contains a design of the same name.' % name
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sys.exit(1)
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print ' - Generating Stratus Model <%s>' % name
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model = module.__dict__[name](name)
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model.Interface()
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if flags & DoNetlist: model.Netlist()
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if flags & DoLayout: model.Layout ()
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stopLevel=0
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if flags & DoStop: stopLevel = 1
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model.View(stopLevel, 'Model %s' % name)
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model.Save(LOGICAL|PHYSICAL)
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except ImportError, e:
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module = str(e).split()[-1]
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print '[ERROR] The <%s> Stratus design cannot be loaded.' % module
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print ' Please check your design hierarchy.'
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2015-03-17 16:50:00 -05:00
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print e
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Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
2015-02-25 15:17:44 -06:00
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sys.exit(1)
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except Exception, e:
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print '[ERROR] A strange exception occurred while loading the Stratus'
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print ' design <%s>. Please check that module for error:\n' % name
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traceback.print_tb(sys.exc_info()[2])
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print ' %s' % e
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sys.exit(2)
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framework = CRL.AllianceFramework.get()
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return framework.getCell( name, CRL.Catalog.State.Views )
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