jcarr
/
coriolis
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
coriolis/crlcore/etc/vsc200/alliance.conf

53 lines
2.2 KiB
Plaintext
Raw Normal View History

Add a common/ to share the trunk of symbolic technologies configurations. In CRL Core configuration files, "display.conf", "patterns.conf" and "technology.conf" share most of their code. So that common part is put into "common/" and sourced from the final configuration file. Update the documentation according the the new initialization scheme.
2014-05-21 17:13:17 -05:00
# -*- Mode:Python; explicit-buffer-name: "alliance.conf<vsc200>" -*-
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00
Added support for multiple symbolic+real technology in configuration. In CRL Core, the layout of the files under "/coriolis2/etc" changes. Instead of having them directly under "etc", they are now replicated, in subdirectories. Each subdirectory having the name of the associated symbolic or real technology (they are kept separated). We have, for now: * etc/cmos/ : symbolic, the Alliance original one. * etc/vsc200/ : symbolic, for G. Petley vsclib. * etc/hcmos9/ : real, generic fake (130nm). To tell which pair (symbolic,real) technologies must be used we create a *second* (sigh) configuration file "coriolis2_techno.conf", and it's hidden counterpart in the user's account, to set it up. It needs to be separate because it is read as early as possible and select which set of configuration files would be read. Also add support up to METAL8 and POLY2 in CRL core and it's Alliance parser/drivers.
2014-05-21 07:50:22 -05:00
cellsTop = '/usr/share/pharosc/alliance/cells/'
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00
allianceConfig = \
Added support for multiple symbolic+real technology in configuration. In CRL Core, the layout of the files under "/coriolis2/etc" changes. Instead of having them directly under "etc", they are now replicated, in subdirectories. Each subdirectory having the name of the associated symbolic or real technology (they are kept separated). We have, for now: * etc/cmos/ : symbolic, the Alliance original one. * etc/vsc200/ : symbolic, for G. Petley vsclib. * etc/hcmos9/ : real, generic fake (130nm). To tell which pair (symbolic,real) technologies must be used we create a *second* (sigh) configuration file "coriolis2_techno.conf", and it's hidden counterpart in the user's account, to set it up. It needs to be separate because it is read as early as possible and select which set of configuration files would be read. Also add support up to METAL8 and POLY2 in CRL core and it's Alliance parser/drivers.
2014-05-21 07:50:22 -05:00
( ( 'SYMB_TECHNO_NAME' , helpers.symbolicTechno )
, ( 'REAL_TECHNO_NAME' , helpers.realTechno )
, ( 'SYMBOLIC_TECHNOLOGY', helpers.symbolicDir+'/technology.conf' )
, ( 'REAL_TECHNOLOGY' , helpers.realDir +'/technology.conf' )
, ( 'DISPLAY' , helpers.sysConfDir +'/display.xml' )
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00
, ( 'CATALOG' , 'CATAL')
, ( 'WORKING_LIBRARY' , '.')
Added support for multiple symbolic+real technology in configuration. In CRL Core, the layout of the files under "/coriolis2/etc" changes. Instead of having them directly under "etc", they are now replicated, in subdirectories. Each subdirectory having the name of the associated symbolic or real technology (they are kept separated). We have, for now: * etc/cmos/ : symbolic, the Alliance original one. * etc/vsc200/ : symbolic, for G. Petley vsclib. * etc/hcmos9/ : real, generic fake (130nm). To tell which pair (symbolic,real) technologies must be used we create a *second* (sigh) configuration file "coriolis2_techno.conf", and it's hidden counterpart in the user's account, to set it up. It needs to be separate because it is read as early as possible and select which set of configuration files would be read. Also add support up to METAL8 and POLY2 in CRL core and it's Alliance parser/drivers.
2014-05-21 07:50:22 -05:00
, ( 'SYSTEM_LIBRARY' , ( (cellsTop+'vsclib' , Environment.Append)
, ) )
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00
, ( 'SCALE_X' , 100)
, ( 'IN_LO' , 'vst')
, ( 'IN_PH' , 'ap')
, ( 'OUT_LO' , 'vst')
, ( 'OUT_PH' , 'ap')
, ( 'POWER' , 'vdd')
, ( 'GROUND' , 'vss')
, ( 'CLOCK' , '^ck.*')
* ./hurricane/doc/hurricane: - Change: In Cell, added doc about PlacementStatus. - Change: In Transformation, more detailed explanations about the orientations. A little beautifying too... - Change: RoutingPad doc update. - Change: Entity doc update (for id). - Change: In HTML header/footer uses the new SoC.css. * ./crlcore/src: - Change: In DefDriver, added support for placement exportation. - New: In Utility, added a "paranoid" output stream (for my extra warnings in the router). - Bug: In ApParser, correct parsing of connectors index (recreate the vector). - Change: In alliance.conf, make "blockageNet" case insensitive. - Change: In misc.conf, added support for paranoid stream. - Change: In x2y and CyclopMain correct verbose flags positionning. * ./crlcore/doc: - Change: Updated style and added some documenation.
2013-12-03 19:47:34 -06:00
, ( 'BLOCKAGE' , '^blockage[Nn]et*')
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00
)
# Format of routingGaugesTable (dictionary):
# A list of entry of the form:
# ( METAL_NAME, (Direction, Type, depth, density, offset, pitch, wire_width, via_width) )
routingGaugesTable = {}
Add a common/ to share the trunk of symbolic technologies configurations. In CRL Core configuration files, "display.conf", "patterns.conf" and "technology.conf" share most of their code. So that common part is put into "common/" and sourced from the final configuration file. Update the documentation according the the new initialization scheme.
2014-05-21 17:13:17 -05:00
routingGaugesTable['vsclib'] = \
ExtensionCap support and source/target terminal flags in Katabatic & Kite. Placement management: * Change: In <metis>, always disable the hMetis support regardless of it being detected or not as the placer is still unable manage the final bin contents. Routing gauge management: * Bug: In CRL Core, <vsclib/alliance.conf>, set the correct pitches and size for the routing layers and the cell gauge. * Change: In Katabatic & Kite, extract the correct extension cap for each routing layer from the layers characteristics (cache then in Katabatic::Configuration). * Change: In Katabatic, <AutoSegment>, create segment with the wire width defined in the gauge. For AutoSegment created on already existing Segment from the global routing, adjust the width. * Change: In Katabatic, <AutoSegment>, more accurate information about how a segment is connected to terminal via source and/or target. The flag SegStrongTerminal is splitted into SegSourceTerminal and SegSourceTarget (but still used as a mask). So now we can know by which end an AutoSegment is connected to a terminal. * Change: In Katabatic, ::doRp_Access(), create constraint freeing segments not only when HSmall but also when VSmall (more critical for <vsclib>). Otherwise we may see AutoSegments with incompatible source/target constraints. * Change: In Kite, BuildPowerRails, do not create blockage on PinOnly layers *but* still create power rails planes. This is a temporary workaround for <vsclib> where the METAL1 blockages overlaps the terminals (it was fine for Nero, but they shouldn't for Kite). * Change: In Kite, <RoutingEvent>, if a TrackSegment is overconstrained, directly bybass it's slackening state to DataNegociate::Slacken. Also rename the flag "_canHandleConstraints" to "_overConstrained", seems clearer to me. Miscellaneous: * Change: In CRL Core, <Utilities>, add a "pass-though" capability on the mstream to temporarily make them print everything.
2014-05-25 08:00:35 -05:00
( ( 'METAL1', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.PinOnly, 0, 0.0, 4, 8, 3, 2 ) )
, ( 'METAL2', ( RoutingLayerGauge.Horizontal, RoutingLayerGauge.Default, 1, 7.0, 0, 8, 4, 2 ) )
, ( 'METAL3', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.Default, 2, 0.0, 4, 8, 4, 2 ) )
, ( 'METAL4', ( RoutingLayerGauge.Horizontal, RoutingLayerGauge.Default, 3, 0.0, 0, 8, 4, 2 ) )
, ( 'METAL5', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.Default, 4, 0.0, 4, 8, 4, 2 ) )
#, ( 'METAL6', ( RoutingLayerGauge.Horizontal, RoutingLayerGauge.Default, 5, 0.0, 0, 8, 4, 2 ) )
#, ( 'METAL7', ( RoutingLayerGauge.Vertical , RoutingLayerGauge.Default, 6, 0.0, 4, 8, 4, 2 ) )
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00
)
# Format of cellGaugesTable (dictionary):
# A list of entry of the form:
# ( METAL_PIN, xy_common_pitch, slice_height, slice_step )
cellGaugesTable = {}
ExtensionCap support and source/target terminal flags in Katabatic & Kite. Placement management: * Change: In <metis>, always disable the hMetis support regardless of it being detected or not as the placer is still unable manage the final bin contents. Routing gauge management: * Bug: In CRL Core, <vsclib/alliance.conf>, set the correct pitches and size for the routing layers and the cell gauge. * Change: In Katabatic & Kite, extract the correct extension cap for each routing layer from the layers characteristics (cache then in Katabatic::Configuration). * Change: In Katabatic, <AutoSegment>, create segment with the wire width defined in the gauge. For AutoSegment created on already existing Segment from the global routing, adjust the width. * Change: In Katabatic, <AutoSegment>, more accurate information about how a segment is connected to terminal via source and/or target. The flag SegStrongTerminal is splitted into SegSourceTerminal and SegSourceTarget (but still used as a mask). So now we can know by which end an AutoSegment is connected to a terminal. * Change: In Katabatic, ::doRp_Access(), create constraint freeing segments not only when HSmall but also when VSmall (more critical for <vsclib>). Otherwise we may see AutoSegments with incompatible source/target constraints. * Change: In Kite, BuildPowerRails, do not create blockage on PinOnly layers *but* still create power rails planes. This is a temporary workaround for <vsclib> where the METAL1 blockages overlaps the terminals (it was fine for Nero, but they shouldn't for Kite). * Change: In Kite, <RoutingEvent>, if a TrackSegment is overconstrained, directly bybass it's slackening state to DataNegociate::Slacken. Also rename the flag "_canHandleConstraints" to "_overConstrained", seems clearer to me. Miscellaneous: * Change: In CRL Core, <Utilities>, add a "pass-though" capability on the mstream to temporarily make them print everything.
2014-05-25 08:00:35 -05:00
cellGaugesTable['vsclib'] = ('metal2', 8.0, 72.0, 8.0)
* All Tools: - A complete sweep of cleanup to suppress allmost all compiler warnings. * ./crlcore: - New: Extented Python support for all objects needed to configure Coriolis. - New: Configuration files and load helpers completly written in Python. An XML emulation mode is still avalaible. - New: UsersGuide, as a replacement for README, written in ReST. - New: Start of Doxygen documentation (mostly for documenting the initialisation objects & methods).
2012-11-16 06:49:47 -06:00