2020-02-03 10:44:15 -06:00
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2020-02-09 11:18:42 -06:00
< title > Symbolic Layout - Coriolis VLSI CAD Tools [offline]< / title >
2020-02-03 10:44:15 -06:00
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2020-02-09 11:18:42 -06:00
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Clarify semantic of flatten Collections (walkthrough).
In the Cell/Instance hierarchy, the "terminal" and "leaf cell" concepts
where not clearly defined and partially overlapping. Now, "Terminal" is
the refer to the physical hierarchy (layout) and "TerminalNetlist" to
the logical hierarchy (netlist). The logical hierarchy can be less deep
than the physical one thanks to a Cell dedicated cell flags. Collections
related to the physical hierarchy keep their old names, the one related
to the logical hierarchy are renamed from "Leaf" to "TerminalNetlist".
The name "Leaf" was too ambiguous (leaf for *what* hierarchy).
* Change: In Hurricane::Device, set the "TerminalNetlist" flag once and
for all. No need set it in all the derived classes again.
* New: In Hurricane::MultiCapacitor, added new parameter "dummy" to
create dummies around the capacity matrix.
* Change: In Hurricane::Cell, remove "Leaf" related methods, replace
them by "TerminalNetlist" one, especially Collections. Now we have
two clear sets of Collections to walkthough the layout or the
netlist.
Change the "Terminal" flag into "TerminalNetlist".
* Change: In Hurricane::CellCollections, rename "Leaf" into
"TerminalNetlist" collections and apply the new semantic to the
locators.
* Change: In Hurricane::DataBase, Leaf to TerminalInstance renaming.
* Change: In Hurricane::DeepNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::HyperNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Instance, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Viewer::HierarchyInformations, Leaf to
TerminalInstance renaming.
* Change: In CRL::AllianceFramework, Leaf to TerminalInstance renaming.
* Change: In CRL::Catalog, Leaf to TerminalInstance renaming.
* Change: In CRL::ApParser, Leaf to TerminalInstance renaming.
* Change: In EtesianEngine::AddFeeds, Leaf to TerminalInstance renaming.
* Bug: In EtesianEngine::resetPlacement, move there the loop over
non terminal netlist instances to flag fully placed sub-blocks
as terminal for the netlist. Only then remove the feed cells
from unplaced instances. Previously, the feed cells where stripped
even from already placed instances.
* Change: In Katana, Leaf to TerminalInstance renaming.
* Bug: In Bora::PyDSlicingNode, allow the range parameter to be the
Python None object when we do not want to pass one but need to
have it as positional parameter.
* Change: In Cumulus/clocktree/ClockTree.py, Leaf to TerminalInstance
renaming.
2020-03-10 06:10:53 -05:00
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2020-02-03 10:44:15 -06:00
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< a class = "pull-left" href = "../" > < img class = "mr20" src = "../images/common/Coriolis-logo-white-4-small.png" alt = "logo" > Coriolis VLSI CAD Tools [offline]< / a >
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Clarify semantic of flatten Collections (walkthrough).
In the Cell/Instance hierarchy, the "terminal" and "leaf cell" concepts
where not clearly defined and partially overlapping. Now, "Terminal" is
the refer to the physical hierarchy (layout) and "TerminalNetlist" to
the logical hierarchy (netlist). The logical hierarchy can be less deep
than the physical one thanks to a Cell dedicated cell flags. Collections
related to the physical hierarchy keep their old names, the one related
to the logical hierarchy are renamed from "Leaf" to "TerminalNetlist".
The name "Leaf" was too ambiguous (leaf for *what* hierarchy).
* Change: In Hurricane::Device, set the "TerminalNetlist" flag once and
for all. No need set it in all the derived classes again.
* New: In Hurricane::MultiCapacitor, added new parameter "dummy" to
create dummies around the capacity matrix.
* Change: In Hurricane::Cell, remove "Leaf" related methods, replace
them by "TerminalNetlist" one, especially Collections. Now we have
two clear sets of Collections to walkthough the layout or the
netlist.
Change the "Terminal" flag into "TerminalNetlist".
* Change: In Hurricane::CellCollections, rename "Leaf" into
"TerminalNetlist" collections and apply the new semantic to the
locators.
* Change: In Hurricane::DataBase, Leaf to TerminalInstance renaming.
* Change: In Hurricane::DeepNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::HyperNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Instance, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Viewer::HierarchyInformations, Leaf to
TerminalInstance renaming.
* Change: In CRL::AllianceFramework, Leaf to TerminalInstance renaming.
* Change: In CRL::Catalog, Leaf to TerminalInstance renaming.
* Change: In CRL::ApParser, Leaf to TerminalInstance renaming.
* Change: In EtesianEngine::AddFeeds, Leaf to TerminalInstance renaming.
* Bug: In EtesianEngine::resetPlacement, move there the loop over
non terminal netlist instances to flag fully placed sub-blocks
as terminal for the netlist. Only then remove the feed cells
from unplaced instances. Previously, the feed cells where stripped
even from already placed instances.
* Change: In Katana, Leaf to TerminalInstance renaming.
* Bug: In Bora::PyDSlicingNode, allow the range parameter to be the
Python None object when we do not want to pass one but need to
have it as positional parameter.
* Change: In Cumulus/clocktree/ClockTree.py, Leaf to TerminalInstance
renaming.
2020-03-10 06:10:53 -05:00
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2020-02-03 10:44:15 -06:00
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< li > < a class = "reference internal" href = "#making-an-asic" id = "id4" > Making an < span class = "sc" > asic< / span > < / a > < / li >
< li > < a class = "reference internal" href = "#id2" id = "id5" > Symbolic Layout< / a > < / li >
< li > < a class = "reference internal" href = "#symbolic-to-real-translation" id = "id6" > Symbolic To Real Translation< / a > < / li >
< li > < a class = "reference internal" href = "#pros-cons-of-symbolic-layout" id = "id7" > Pros & Cons of Symbolic Layout< / a > < / li >
< li > < a class = "reference internal" href = "#a-note-about-analog-designs" id = "id8" > A Note About Analog Designs< / a > < / li >
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< h2 > < a class = "toc-backref" href = "#id4" > Making an < span class = "sc" > asic< / span > < / a > < / h2 >
< p > This section is a short introduction to the terminology of < span class = "sc" > asic< / span > making.< / p >
< p > The end product of a < span class = "sc" > vlsi< / span > design flow is basically a < em > drawing< / em > . This drawing
is what you send to the foundry in order to fabricate it. Usually, this is a
file in < span class = "sc" > gds< / span > format, which contains a lot of geometric shapes expressed in
microns or nanometers.< / p >
< p > This drawing is called a < strong > layout< / strong > .< / p >
< p > In the layout, each geometrical shape is associated with a < em > layer< / em > . For example,
there are layers for each metal level like < tt class = "docutils literal" > metal1< / tt > or < tt class = "docutils literal" > metal2< / tt > .< / p >
< p > < strong > Layers< / strong > tells in what < em > material< / em > you want the geometrical shape to be build.
(this is an oversimplification)< / p >
< p > All shapes in a given layer constitute a < strong > mask< / strong > , analogous to an overlay in
classical drawing programs.< / p >
< p > The foundry will not accept < em > any< / em > layout. In order to be successfully fabricated,
all the shapes of a layout must respect a set of rules. For example, to ensure
that after fabrication, two separated shapes of < tt class = "docutils literal" > metal1< / tt > are indeed separated,
they must respect a < em > minimal distance< / em > , for example 0.5µ. This special set of
rules is called the < strong > Design rules< / strong > .< / p >
< p > < strong > Design Rules< / strong > gives many insigth about a process and is subjected to < span class = "sc" > nda< / span > .
For the same reason your whole layout covered by it, meaning that you cannot
publish it in any way.< / p >
< / div >
< div class = "section" id = "id2" >
< h2 > < a class = "toc-backref" href = "#id5" > Symbolic Layout< / a > < / h2 >
< p > < strong > Symbolic Layout< / strong > is a way of making the layout of a chip independant of a given
technological node. This technique is based on the observation that, between two
processes in the same technological node (say, for example, 350nm of < span class = "sc" > ams< / span > and
350nm of < span class = "sc" > tsmc< / span > ), there are only minors rules variations. Moreover, even between
different nodes (350nm < span class = "sc" > ams< / span > and 180nm < span class = "sc" > ams< / span > ), the < em > shrink rate< / em > of the various
layers of the process are the same.< / p >
< p > Symbolic layout consist of drawing in a blank unit called the < span class = "raw-html" > & #955< / span > (lambda).
Then, the value of the < span class = "raw-html" > & #955< / span > is calculated for the target technology so that the
layout fit it's particular design rules. This approach was first introduced by
< span class = "sc" > Mead< / span > & < span class = "sc" > Conway< / span > < a class = "citation-reference" href = "#vlsisys" id = "id3" > [VLSISYS]< / a > .< / p >
< p > As < span class = "sc" > Coriolis< / span > can manage both symbolic and real layers in the same design,
it uses the following convention for layer naming:< / p >
< ul class = "simple" >
< li > < tt class = "docutils literal" > METAL1< / tt > : uppercase named layers are for < em > symbolic layers< / em > . Those layer
shapes will change when mapped toward a real technology.< / li >
< li > < tt class = "docutils literal" > metal1< / tt > : lowercase named layers are for < em > real layers< / em > . THeir shapes will
be exported exacltly < em > as is< / em > .< / li >
< / ul >
< p > < img alt = "Symbolic, Mead & Conway" class = "align-middle" src = "../images/symbolic-layout/symbolic-1.png" style = "width: 80%;" / > < / p >
< p > The symbolic layout of < span class = "sc" > Alliance< / span > , refine this approach, by adding width and cap
extentions factors to allow a closer fitting of the technology.< / p >
< p > < img alt = "Symbolic, Alliance" class = "align-middle" src = "../images/symbolic-layout/symbolic-2.png" style = "width: 80%;" / > < / p >
< / div >
< div class = "section" id = "symbolic-to-real-translation" >
< h2 > < a class = "toc-backref" href = "#id6" > Symbolic To Real Translation< / a > < / h2 >
< p > Contrary to commercial design flows wich directly creates a layout for a target
node, our flow create a < em > symbolic layout< / em > which you have to translate into one
on the target process. This is done with the < span class = "cb" > s2r< / span > tool which stands for
" Symbolic To Real" . And this tool must have a configuration file for the
intended technology (this is the < tt class = "docutils literal" > .rds< / tt > file). As the < tt class = "docutils literal" > .rds< / tt > file is
written using the < strong > Design Rules< / strong > so is under < span class = "sc" > nda< / span > . Writting the < tt class = "docutils literal" > .rds< / tt >
to get the best fit for target process is still largely a craft.< / p >
< p > < img alt = "Symbolic to Real translation" class = "align-middle" src = "../images/symbolic-layout/rds-1.png" style = "width: 80%;" / > < / p >
< / div >
< div class = "section" id = "pros-cons-of-symbolic-layout" >
< h2 > < a class = "toc-backref" href = "#id7" > Pros & Cons of Symbolic Layout< / a > < / h2 >
< p > Cons:< / p >
< ul class = "simple" >
< li > As it cannot make use of the finest features of the target process, there is an
unvoidable loss of area. That is, the layout once translated will be bigger than
if it has been done directly. The loss is below 10%.< / li >
< / ul >
< p > Pros:< / p >
< ul class = "simple" >
< li > You do not have to build you chip for each target process. You only need to write
a new < tt class = "docutils literal" > .rds< / tt > file.< / li >
< li > Symbolic layout is not subjected to < span class = "sc" > nda< / span > , so it can be freely published and
exchanged.< / li >
< / ul >
< / div >
< div class = "section" id = "a-note-about-analog-designs" >
< h2 > < a class = "toc-backref" href = "#id8" > A Note About Analog Designs< / a > < / h2 >
< p > The symbolic layout approach is not suited for analog designs. Analog designs are
closely related to the target process. So we developped a different methodology
to ensure portability.< / p >
< table class = "docutils citation" frame = "void" id = "vlsisys" rules = "none" >
< colgroup > < col class = "label" / > < col / > < / colgroup >
< tbody valign = "top" >
< tr > < td class = "label" > < a class = "fn-backref" href = "#id3" > [VLSISYS]< / a > < / td > < td > < span class = "sc" > Mead< / span > , Carver; < span class = "sc" > Conway< / span > , Lynn (1980). Introduction to VLSI systems.
Reading, Mass.: Addison-Wesley. ISBN 0201043580. OCLC 4641561< / td > < / tr >
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