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<h1 class="header-title text-uppercase">Symbolic Layout</h1>
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<!-- -*- Mode: rst -*- -->
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<!-- -*- Mode: rst; explicit-buffer-name: "definition.rst<documentation/etc>" -*- -->
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<div class="contents topic" id="contents">
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<p class="topic-title first">Contents</p>
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<ul class="simple">
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<li><a class="reference internal" href="#making-an-asic" id="id4">Making an <span class="sc">asic</span></a></li>
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<li><a class="reference internal" href="#id2" id="id5">Symbolic Layout</a></li>
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<li><a class="reference internal" href="#symbolic-to-real-translation" id="id6">Symbolic To Real Translation</a></li>
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<li><a class="reference internal" href="#pros-cons-of-symbolic-layout" id="id7">Pros & Cons of Symbolic Layout</a></li>
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<li><a class="reference internal" href="#a-note-about-analog-designs" id="id8">A Note About Analog Designs</a></li>
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</ul>
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</div>
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<div class="section" id="making-an-asic">
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<h2><a class="toc-backref" href="#id4">Making an <span class="sc">asic</span></a></h2>
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<p>This section is a short introduction to the terminology of <span class="sc">asic</span> making.</p>
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<p>The end product of a <span class="sc">vlsi</span> design flow is basically a <em>drawing</em>. This drawing
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is what you send to the foundry in order to fabricate it. Usually, this is a
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file in <span class="sc">gds</span> format, which contains a lot of geometric shapes expressed in
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microns or nanometers.</p>
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<p>This drawing is called a <strong>layout</strong>.</p>
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<p>In the layout, each geometrical shape is associated with a <em>layer</em>. For example,
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there are layers for each metal level like <tt class="docutils literal">metal1</tt> or <tt class="docutils literal">metal2</tt>.</p>
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<p><strong>Layers</strong> tells in what <em>material</em> you want the geometrical shape to be build.
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(this is an oversimplification)</p>
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<p>All shapes in a given layer constitute a <strong>mask</strong>, analogous to an overlay in
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classical drawing programs.</p>
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<p>The foundry will not accept <em>any</em> layout. In order to be successfully fabricated,
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all the shapes of a layout must respect a set of rules. For example, to ensure
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that after fabrication, two separated shapes of <tt class="docutils literal">metal1</tt> are indeed separated,
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they must respect a <em>minimal distance</em>, for example 0.5µ. This special set of
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rules is called the <strong>Design rules</strong>.</p>
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<p><strong>Design Rules</strong> gives many insigth about a process and is subjected to <span class="sc">nda</span>.
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For the same reason your whole layout covered by it, meaning that you cannot
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publish it in any way.</p>
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</div>
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<div class="section" id="id2">
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<h2><a class="toc-backref" href="#id5">Symbolic Layout</a></h2>
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<p><strong>Symbolic Layout</strong> is a way of making the layout of a chip independant of a given
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technological node. This technique is based on the observation that, between two
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processes in the same technological node (say, for example, 350nm of <span class="sc">ams</span> and
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350nm of <span class="sc">tsmc</span>), there are only minors rules variations. Moreover, even between
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different nodes (350nm <span class="sc">ams</span> and 180nm <span class="sc">ams</span>), the <em>shrink rate</em> of the various
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layers of the process are the same.</p>
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<p>Symbolic layout consist of drawing in a blank unit called the <span class="raw-html">λ</span> (lambda).
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Then, the value of the <span class="raw-html">λ</span> is calculated for the target technology so that the
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layout fit it's particular design rules. This approach was first introduced by
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<span class="sc">Mead</span> & <span class="sc">Conway</span> <a class="citation-reference" href="#vlsisys" id="id3">[VLSISYS]</a>.</p>
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<p>As <span class="sc">Coriolis</span> can manage both symbolic and real layers in the same design,
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it uses the following convention for layer naming:</p>
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<ul class="simple">
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<li><tt class="docutils literal">METAL1</tt> : uppercase named layers are for <em>symbolic layers</em>. Those layer
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shapes will change when mapped toward a real technology.</li>
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<li><tt class="docutils literal">metal1</tt> : lowercase named layers are for <em>real layers</em>. THeir shapes will
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be exported exacltly <em>as is</em>.</li>
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</ul>
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<p><img alt="Symbolic, Mead & Conway" class="align-middle" src="../images/symbolic-layout/symbolic-1.png" style="width: 80%;" /></p>
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<p>The symbolic layout of <span class="sc">Alliance</span>, refine this approach, by adding width and cap
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extentions factors to allow a closer fitting of the technology.</p>
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<p><img alt="Symbolic, Alliance" class="align-middle" src="../images/symbolic-layout/symbolic-2.png" style="width: 80%;" /></p>
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</div>
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<div class="section" id="symbolic-to-real-translation">
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<h2><a class="toc-backref" href="#id6">Symbolic To Real Translation</a></h2>
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<p>Contrary to commercial design flows wich directly creates a layout for a target
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node, our flow create a <em>symbolic layout</em> which you have to translate into one
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on the target process. This is done with the <span class="cb">s2r</span> tool which stands for
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"Symbolic To Real". And this tool must have a configuration file for the
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intended technology (this is the <tt class="docutils literal">.rds</tt> file). As the <tt class="docutils literal">.rds</tt> file is
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written using the <strong>Design Rules</strong> so is under <span class="sc">nda</span>. Writting the <tt class="docutils literal">.rds</tt>
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to get the best fit for target process is still largely a craft.</p>
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<p><img alt="Symbolic to Real translation" class="align-middle" src="../images/symbolic-layout/rds-1.png" style="width: 80%;" /></p>
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</div>
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<div class="section" id="pros-cons-of-symbolic-layout">
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<h2><a class="toc-backref" href="#id7">Pros & Cons of Symbolic Layout</a></h2>
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<p>Cons:</p>
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<ul class="simple">
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<li>As it cannot make use of the finest features of the target process, there is an
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unvoidable loss of area. That is, the layout once translated will be bigger than
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if it has been done directly. The loss is below 10%.</li>
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</ul>
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<p>Pros:</p>
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<ul class="simple">
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<li>You do not have to build you chip for each target process. You only need to write
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a new <tt class="docutils literal">.rds</tt> file.</li>
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<li>Symbolic layout is not subjected to <span class="sc">nda</span>, so it can be freely published and
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exchanged.</li>
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</ul>
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</div>
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<div class="section" id="a-note-about-analog-designs">
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<h2><a class="toc-backref" href="#id8">A Note About Analog Designs</a></h2>
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<p>The symbolic layout approach is not suited for analog designs. Analog designs are
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closely related to the target process. So we developped a different methodology
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to ensure portability.</p>
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<table class="docutils citation" frame="void" id="vlsisys" rules="none">
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<colgroup><col class="label" /><col /></colgroup>
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<tbody valign="top">
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<tr><td class="label"><a class="fn-backref" href="#id3">[VLSISYS]</a></td><td><span class="sc">Mead</span>, Carver; <span class="sc">Conway</span>, Lynn (1980). Introduction to VLSI systems.
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Reading, Mass.: Addison-Wesley. ISBN 0201043580. OCLC 4641561</td></tr>
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</tbody>
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