92 lines
3.9 KiB
TeX
92 lines
3.9 KiB
TeX
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\begin{itemize}
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\item \textbf{Name} : DpgenFifo -- Fifo Macro-Generator
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\item \textbf{Synopsys} :
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\begin{verbatim}
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Generate ( 'DpgenFifo', modelname
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, param = { 'nbit' : n
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, 'nword' : regNumber
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, 'physical' : True
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}
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)
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\end{verbatim}
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\item \textbf{Description} : Generates a FIFO of \verb-regNumber- words of \verb-n- bits named \verb-modelname-.
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\item \textbf{Terminal Names} :
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\begin{itemize}
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\item \textbf{ck} : clock signal (input, 1 bit)
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\item \textbf{reset} : reset signal (input, 1 bit)
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\item \textbf{r} : read requested (input, 1 bit)
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\item \textbf{w} : write requested (input, 1 bit)
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\item \textbf{rok} : read acknowledge (output, 1 bit)
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\item \textbf{wok} : write acknowledge (output, 1 bit)
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\item \textbf{sel} : select the write bus (input, 1 bit)
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\item \textbf{datain0} : first write bus (input, \verb-n- bits)
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\item \textbf{datain1} : second write bus (input, \verb-n- bits)
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\item \textbf{dataout} : read bus (output, \verb-n- bits)
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\item \textbf{vdd} : power
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\item \textbf{vss} : ground
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\end{itemize}
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\item \textbf{Parameters} : Parameters are given in the map \verb-param-.
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\begin{itemize}
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\item \textbf{nbit} (mandatory) : Defines the size of the words (even, between 2 and 64)
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\item \textbf{nword} (mandatory) : Defines the number of words (even, between 4 and 32)
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\item \textbf{physical} (optional, default value : False) : In order to generate a layout
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\end{itemize}
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\item \textbf{How it works} :
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\begin{itemize}
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\item datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal.
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\item sel : when set to \verb-zero- the datain0 is used to write the register word, otherwise it will be datain1.
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\item r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty).
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\item w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full).
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\end{itemize}
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% \item \textbf{Behavior} :
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%\begin{verbatim}
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%\end{verbatim}
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\item \textbf{Example} :
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\begin{verbatim}
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from stratus import *
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class inst_fifo ( Model ) :
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def Interface ( self ) :
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self.ck = SignalIn ( "ck", 1 )
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self.reset = SignalIn ( "reset", 1 )
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self.r = SignalIn ( "r", 1 )
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self.w = SignalIn ( "w", 1 )
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self.rok = SignalInOut ( "rok", 1 )
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self.wok = SignalInOut ( "wok", 1 )
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self.sel = SignalIn ( "sel", 1 )
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self.datain0 = SignalIn ( "datain0", 4 )
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self.datain1 = SignalIn ( "datain1", 4 )
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self.dataout = SignalOut ( "dataout", 4 )
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self.vdd = VddIn ( "vdd" )
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self.vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Generate ( 'DpgenFifo', 'fifo_4_16'
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, param = { 'nbit' : 4
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, 'nword' : 16
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, 'physical' : True
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}
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)
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self.I = Inst ( 'fifo_4_16', 'inst'
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, map = { 'ck' : self.ck
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, 'reset' : self.reset
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, 'r' : self.r
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, 'w' : self.w
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, 'rok' : self.rok
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, 'wok' : self.wok
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, 'sel' : self.sel
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, 'datain0' : self.datain0
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, 'datain1' : self.datain1
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, 'dataout' : self.dataout
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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def Layout ( self ) :
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Place ( self.I, NOSYM, Ref(0, 0) )
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\end{verbatim}
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\end{itemize}
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