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Jean-Paul Chaput 205a6877db More generic H-Tree support to accomodate the LS180 PLL internal clock. 
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.

* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
    of the function to allow the user to select nets that will *not*
    be flattened. This makes the NoClockFlatten flag effectively obsolete,
    we keep it for backward compatibility.
      The net names can be of non top level ones. In that case, they must
    use the name an HyperNet will get (the Occurrence name). For example:
         "instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
    new utility function pyListToStringSet() to translate a Python list into
    a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
    from the flattening procedure. Those excluded nets will also be
    excludeds from the Coloquinte nets *and* HFNS synthesis, as they
    are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
    flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
    on nets that are already fixed or detaled route. This replace the
    clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
    of clock-tree by the more generic H-Tree. That is, we can ask the P&R
    to create H-Tree on any net of the design, not only the ones matcheds
    as clock. The net does not even need to be top-level.
      This is to manage the PLL internal clock generated by the PLL in
    the LS180 chip.
      Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
    there was an inversion of the H & V routing gauges to compute the
    track into which put the H-Tree center to corona edge wiring.
      This was causing tracks to be used twice, seen in the ao68000 test
    bench.
 		2021-05-31 00:02:23 +02:00
anabatic More generic H-Tree support to accomodate the LS180 PLL internal clock. 2021-05-31 00:02:23 +02:00
bootstrap Don't remembers what thoses do, but don't want to loose them either. 2021-04-21 17:00:48 +02:00
bora Bug fix, reset Cell flags after unrouting an analog design. 2020-04-30 00:38:32 +02:00
coloquinte Add updators to modify cell sizes on the fly in Coloquinte. 2021-01-13 19:10:31 +01:00
crlcore Add & fix GDS parser for PATH of type 4 (seen in the PLL). 2021-05-25 15:08:57 +02:00
cumulus More generic H-Tree support to accomodate the LS180 PLL internal clock. 2021-05-31 00:02:23 +02:00
documentation Updated PDFs, November 13, 2020 (15:02). 2020-11-13 15:02:56 +01:00
equinox Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
etesian More generic H-Tree support to accomodate the LS180 PLL internal clock. 2021-05-31 00:02:23 +02:00
flute Added support for loading user defined global routing in Anabatic. 2020-09-30 11:55:39 +02:00
hurricane More generic H-Tree support to accomodate the LS180 PLL internal clock. 2021-05-31 00:02:23 +02:00
ispd Various typos correction (courtesy of G. Gouvine). 2019-07-30 13:13:57 +02:00
karakaze Correct Cell object detection while reading Oceane parameters. 2020-05-27 16:11:53 +02:00
katabatic Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
katana Ignore short overlaping same-net segments in realign stage. 2021-05-11 14:30:10 +02:00
kite Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
knik Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
lefdef Migrating doc from Sphinx towards Pelican. 2020-02-03 17:44:15 +01:00
mauka Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
metis Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
nimbus Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
oroshi Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
solstice Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
stratus1 Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
tutorial More PEP8 compliant Python code. Start rewrite Python/C++ wrappers. 2020-04-08 11:24:42 +02:00
unicorn Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
unittests Enhanced techno rule support. Inspector support bug fix. 2020-07-21 11:22:04 +02:00
vlsisapd Fix unitialized stat structure in Vlsisapd, Path::mode() (valgrind). 2021-05-11 13:46:53 +02:00
.gitignore Various bug corrections to pass the alliance-check-toolkit reference benchs. 2019-05-24 23:57:22 +02:00
Makefile Enabling the user to choose the devtoolset it needs. 2019-03-04 14:20:13 +01:00
README.rst Update doc link for the new Pelican generated one. 2020-02-10 13:38:06 +01:00

README.rst 

.. -*- Mode: rst -*-


===============
Coriolis README
===============

Coriolis is a free database, placement tool and routing tool for VLSI design.


Purpose
=======

Coriolis provides several tools to perform the layout of VLSI circuits.  Its
main components are the Hurricane database, the Etesian placer and the Katana
router, but other tools can use the Hurricane database and the parsers
provided.

The user interface <cgt> is the prefered way to use Coriolis, but all
Coriolis tools are Python modules and thus scriptable.


Documentation
=============

The complete documentation is available here, both in pdf & html:

   ./documentation/output/html
   ./documentation/UsersGuide/UsersGuide.pdf

The documentation of the latest *stable* version is also
available online. It may be quite outdated from the *devel*
version.

    https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/en/latex/users-guide/UsersGuide.pdf


Building Coriolis
=================

To build Coriolis, ensure the following prerequisites are met:

* Python 2.7.
* cmake.
* boost.
* bison & flex.
* Qt 4 or 5.
* libxml2.
* RapidJSON
* A C++11 compliant compiler.

The build system relies on a fixed directory tree from the root
of the user currently building it. Thus first step is to get a clone of
the repository in the right place. Proceed as follow: ::

   ego@home:~$ mkdir -p ~/coriolis-2.x/src/support
   ego@home:~$ cd ~/coriolis-2.x/src/support
   ego@home:~$ git clone http://github.com/miloyip/rapidjson
   ego@home:~$ git checkout ec322005072076ef53984462fb4a1075c27c7dfd
   ego@home:~$ cd ~/coriolis-2.x/src
   ego@home:src$ git clone https://www-soc.lip6.fr/git/coriolis.git
   ego@home:src$ cd coriolis

If you want to use the *devel* branch: ::

    ego@home:coriolis$ git checkout devel

Then, build the tool: ::

    ego@home:coriolis$ make install

Coriolis gets installed at the root of the following tree: ::

    ~/coriolis-2.x/<OS>.<DISTRIB>/Release.Shared/install/

Where ``<OS>`` is the name of your operating system and ``<DISTRIB>`` your
distribution.


Using Coriolis
==============

The Coriolis main interface can be launched with the command: ::

    ego@home:~: ~/coriolis-2.x/<OS>.<DISTRIB>/Release.Shared/install/bin/coriolis

The ``coriolis`` script detects its location and setups the UNIX
environment appropriately, then lauches ``cgt`` (or *any* command, with the
``--run=<COMMAND>`` option).

Conversely, you can setup the current shell environement for Coriolis by 
using the helper ``coriolisEnv.py``, then run any Coriolis tool: ::

    ego@home:~$ eval `~/coriolis-2.x/src/coriolis/bootstrap/coriolisEnv.py`
    ego@home:~$ cgt -V