Initial import of BIST build, to share
This commit is contained in:
Mark Coldebella
parent
1717cd4af8
commit
6b13247811
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@ -0,0 +1,16 @@
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This project is compiled with the following Vivado version
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Vivado v2017.4 (64-bit)
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SW Build: 2086221 on Fri Dec 15 20:55:39 MST 2017
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IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017
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It uses two Xilinx IP modules that require temporary hardware licenses
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axi_ethernet_0 AXI 1G/2.5G Ethernet Subsystem:7.1
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axi_usb2_device_0 AXI USB2 Device:5.0
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From the command line
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Go to the directory this file is in
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Type vivado -mode tcl
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At the vivado prompt
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Type source bist_sha256.tcl
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The project will be built in the bist_sha256 directory
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,100 @@
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set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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set_property CONFIG_MODE BPI16 [current_design]
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]system.xdc
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set_property PACKAGE_PIN AY32 [get_ports ULPI_clk]
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set_property IOSTANDARD LVCMOS18 [get_ports ULPI_clk]
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set_property PACKAGE_PIN BB33 [get_ports ULPI_dir]
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set_property IOSTANDARD LVCMOS18 [get_ports ULPI_dir]
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set_property PACKAGE_PIN BA35 [get_ports ULPI_next]
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set_property IOSTANDARD LVCMOS18 [get_ports ULPI_next]
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set_property PACKAGE_PIN BB36 [get_ports ULPI_rst]
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set_property IOSTANDARD LVCMOS18 [get_ports ULPI_rst]
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set_property PACKAGE_PIN BB32 [get_ports ULPI_stop]
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set_property IOSTANDARD LVCMOS18 [get_ports ULPI_stop]
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set_property PACKAGE_PIN AV36 [get_ports {ULPI_data_io[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[0]}]
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set_property PACKAGE_PIN AW36 [get_ports {ULPI_data_io[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[1]}]
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set_property PACKAGE_PIN BA34 [get_ports {ULPI_data_io[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[2]}]
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set_property PACKAGE_PIN BB34 [get_ports {ULPI_data_io[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[3]}]
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set_property PACKAGE_PIN BA36 [get_ports {ULPI_data_io[4]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[4]}]
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set_property PACKAGE_PIN AT34 [get_ports {ULPI_data_io[5]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[5]}]
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set_property PACKAGE_PIN AY35 [get_ports {ULPI_data_io[6]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[6]}]
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set_property PACKAGE_PIN AW35 [get_ports {ULPI_data_io[7]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[7]}]
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set_property PACKAGE_PIN AY42 [get_ports {iic_mux_reset_b[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {iic_mux_reset_b[0]}]
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set_property PACKAGE_PIN AT36 [get_ports {iic_mux_reset_b[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {iic_mux_reset_b[1]}]
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set_property PACKAGE_PIN AN38 [get_ports Vaux0_v_p]
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set_property IOSTANDARD LVCMOS18 [get_ports Vaux0_v_p]
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set_property PACKAGE_PIN AP38 [get_ports Vaux0_v_n]
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set_property IOSTANDARD LVCMOS18 [get_ports Vaux0_v_n]
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set_property PACKAGE_PIN AM41 [get_ports Vaux8_v_p]
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set_property IOSTANDARD LVCMOS18 [get_ports Vaux8_v_p]
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set_property PACKAGE_PIN AM42 [get_ports Vaux8_v_n]
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set_property IOSTANDARD LVCMOS18 [get_ports Vaux8_v_n]
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set_property PACKAGE_PIN BA37 [get_ports SM_FAN_PWM]
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set_property IOSTANDARD LVCMOS18 [get_ports SM_FAN_PWM]
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set_property PACKAGE_PIN AD8 [get_ports SI5324_IN_clk_p]
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set_property PACKAGE_PIN AK34 [get_ports USER_CLOCK_IN_clk_p]
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set_property IOSTANDARD LVDS [get_ports USER_CLOCK_IN_clk_p]
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set_property PACKAGE_PIN AW32 [get_ports SI5324_OUT_clk_p]
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set_property IOSTANDARD LVDS [get_ports SI5324_OUT_clk_p]
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set_property PACKAGE_PIN AN31 [get_ports SMA_OUT_clk_p]
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set_property IOSTANDARD LVDS [get_ports SMA_OUT_clk_p]
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set_property PACKAGE_PIN G19 [get_ports DDR3_CLK1_P]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_CLK1_P]
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set_property PACKAGE_PIN F19 [get_ports DDR3_CLK1_N]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_CLK1_N]
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set_property PACKAGE_PIN J18 [get_ports DDR3_CKE1]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
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set_property PACKAGE_PIN J20 [get_ports DDR3_S1_B]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
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set_property PACKAGE_PIN H18 [get_ports DDR3_ODT1]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
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set_property PACKAGE_PIN F17 [get_ports DDR3_A14]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
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set_property PACKAGE_PIN E17 [get_ports DDR3_A15]
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set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
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@ -0,0 +1,354 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com"
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>gtxe2_top</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>SI5324_OUT</spirit:name>
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<spirit:displayName>user_clock</spirit:displayName>
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<spirit:busType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock"
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spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock_rtl"
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spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_P</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>si5324_out_p</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_N</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>si5324_out_n</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>SMA_OUT</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock"
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spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock_rtl"
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spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_P</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>SMA_out_p</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_N</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>SMA_out_n</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>USER_CLOCK_IN</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock"
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spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock_rtl"
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spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_P</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>user_clock_p</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_N</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>user_clock_n</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>SI5324_IN</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock"
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spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com"
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spirit:library="interface"
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spirit:name="diff_clock_rtl"
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spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_P</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>si5324_in_p</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK_N</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>si5324_in_n</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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</spirit:busInterfaces>
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||||||
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<spirit:model>
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<spirit:views>
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<spirit:view>
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||||||
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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||||||
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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||||||
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>gtxe2_top</spirit:modelName>
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<spirit:fileSetRef>
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||||||
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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||||||
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</spirit:fileSetRef>
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||||||
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<spirit:parameters>
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||||||
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<spirit:parameter>
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||||||
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<spirit:name>viewChecksum</spirit:name>
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||||||
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<spirit:value>0a690b65</spirit:value>
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||||||
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</spirit:parameter>
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||||||
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</spirit:parameters>
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||||||
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</spirit:view>
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||||||
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<spirit:view>
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||||||
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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||||||
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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||||||
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||||
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<spirit:language>verilog</spirit:language>
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||||||
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<spirit:modelName>gtxe2_top</spirit:modelName>
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||||||
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<spirit:fileSetRef>
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||||||
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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||||||
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</spirit:fileSetRef>
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||||||
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<spirit:parameters>
|
||||||
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<spirit:parameter>
|
||||||
|
<spirit:name>viewChecksum</spirit:name>
|
||||||
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<spirit:value>0a690b65</spirit:value>
|
||||||
|
</spirit:parameter>
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||||||
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</spirit:parameters>
|
||||||
|
</spirit:view>
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||||||
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<spirit:view>
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||||||
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<spirit:name>xilinx_xpgui</spirit:name>
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||||||
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<spirit:displayName>UI Layout</spirit:displayName>
|
||||||
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||||
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<spirit:fileSetRef>
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||||||
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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||||||
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</spirit:fileSetRef>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>viewChecksum</spirit:name>
|
||||||
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<spirit:value>f64a5dae</spirit:value>
|
||||||
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</spirit:parameter>
|
||||||
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</spirit:parameters>
|
||||||
|
</spirit:view>
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||||||
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</spirit:views>
|
||||||
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<spirit:ports>
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||||||
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<spirit:port>
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||||||
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<spirit:name>user_clock_p</spirit:name>
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||||||
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<spirit:wire>
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||||||
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<spirit:direction>in</spirit:direction>
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||||||
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<spirit:wireTypeDefs>
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||||||
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<spirit:wireTypeDef>
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||||||
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<spirit:typeName>std_logic</spirit:typeName>
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||||||
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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||||||
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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||||||
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</spirit:wireTypeDef>
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||||||
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</spirit:wireTypeDefs>
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||||||
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</spirit:wire>
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||||||
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</spirit:port>
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||||||
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<spirit:port>
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||||||
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<spirit:name>user_clock_n</spirit:name>
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||||||
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<spirit:wire>
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||||||
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<spirit:direction>in</spirit:direction>
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||||||
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<spirit:wireTypeDefs>
|
||||||
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<spirit:wireTypeDef>
|
||||||
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<spirit:typeName>std_logic</spirit:typeName>
|
||||||
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
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</spirit:wireTypeDef>
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||||||
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</spirit:wireTypeDefs>
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||||||
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</spirit:wire>
|
||||||
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</spirit:port>
|
||||||
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<spirit:port>
|
||||||
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<spirit:name>si5324_out_p</spirit:name>
|
||||||
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<spirit:wire>
|
||||||
|
<spirit:direction>out</spirit:direction>
|
||||||
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<spirit:wireTypeDefs>
|
||||||
|
<spirit:wireTypeDef>
|
||||||
|
<spirit:typeName>std_logic</spirit:typeName>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
|
</spirit:wireTypeDef>
|
||||||
|
</spirit:wireTypeDefs>
|
||||||
|
</spirit:wire>
|
||||||
|
</spirit:port>
|
||||||
|
<spirit:port>
|
||||||
|
<spirit:name>si5324_out_n</spirit:name>
|
||||||
|
<spirit:wire>
|
||||||
|
<spirit:direction>out</spirit:direction>
|
||||||
|
<spirit:wireTypeDefs>
|
||||||
|
<spirit:wireTypeDef>
|
||||||
|
<spirit:typeName>std_logic</spirit:typeName>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
|
</spirit:wireTypeDef>
|
||||||
|
</spirit:wireTypeDefs>
|
||||||
|
</spirit:wire>
|
||||||
|
</spirit:port>
|
||||||
|
<spirit:port>
|
||||||
|
<spirit:name>si5324_in_p</spirit:name>
|
||||||
|
<spirit:wire>
|
||||||
|
<spirit:direction>in</spirit:direction>
|
||||||
|
<spirit:wireTypeDefs>
|
||||||
|
<spirit:wireTypeDef>
|
||||||
|
<spirit:typeName>std_logic</spirit:typeName>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
|
</spirit:wireTypeDef>
|
||||||
|
</spirit:wireTypeDefs>
|
||||||
|
</spirit:wire>
|
||||||
|
</spirit:port>
|
||||||
|
<spirit:port>
|
||||||
|
<spirit:name>si5324_in_n</spirit:name>
|
||||||
|
<spirit:wire>
|
||||||
|
<spirit:direction>in</spirit:direction>
|
||||||
|
<spirit:wireTypeDefs>
|
||||||
|
<spirit:wireTypeDef>
|
||||||
|
<spirit:typeName>std_logic</spirit:typeName>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
|
</spirit:wireTypeDef>
|
||||||
|
</spirit:wireTypeDefs>
|
||||||
|
</spirit:wire>
|
||||||
|
</spirit:port>
|
||||||
|
<spirit:port>
|
||||||
|
<spirit:name>SMA_out_p</spirit:name>
|
||||||
|
<spirit:wire>
|
||||||
|
<spirit:direction>out</spirit:direction>
|
||||||
|
<spirit:wireTypeDefs>
|
||||||
|
<spirit:wireTypeDef>
|
||||||
|
<spirit:typeName>std_logic</spirit:typeName>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
|
</spirit:wireTypeDef>
|
||||||
|
</spirit:wireTypeDefs>
|
||||||
|
</spirit:wire>
|
||||||
|
</spirit:port>
|
||||||
|
<spirit:port>
|
||||||
|
<spirit:name>SMA_out_n</spirit:name>
|
||||||
|
<spirit:wire>
|
||||||
|
<spirit:direction>out</spirit:direction>
|
||||||
|
<spirit:wireTypeDefs>
|
||||||
|
<spirit:wireTypeDef>
|
||||||
|
<spirit:typeName>std_logic</spirit:typeName>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||||
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||||
|
</spirit:wireTypeDef>
|
||||||
|
</spirit:wireTypeDefs>
|
||||||
|
</spirit:wire>
|
||||||
|
</spirit:port>
|
||||||
|
</spirit:ports>
|
||||||
|
</spirit:model>
|
||||||
|
<spirit:fileSets>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>src/gtxe2_top.v</spirit:name>
|
||||||
|
<spirit:fileType>verilogSource</spirit:fileType>
|
||||||
|
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||||
|
<spirit:userFileType>CHECKSUM_0a690b65</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>src/gtxe2_top.v</spirit:name>
|
||||||
|
<spirit:fileType>verilogSource</spirit:fileType>
|
||||||
|
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>xgui/gtxe2_top_v1_0.tcl</spirit:name>
|
||||||
|
<spirit:fileType>tclSource</spirit:fileType>
|
||||||
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||||
|
<spirit:userFileType>CHECKSUM_f92e9879</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
|
</spirit:fileSets>
|
||||||
|
<spirit:description>gtxe2_top_v1_0</spirit:description>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>Component_Name</spirit:name>
|
||||||
|
<spirit:value spirit:resolve="user"
|
||||||
|
spirit:id="PARAM_VALUE.Component_Name"
|
||||||
|
spirit:order="1">gtxe2_top_v1_0</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
<spirit:vendorExtensions>
|
||||||
|
<xilinx:coreExtensions>
|
||||||
|
<xilinx:supportedFamilies>
|
||||||
|
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||||
|
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||||
|
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||||
|
</xilinx:supportedFamilies>
|
||||||
|
<xilinx:taxonomies>
|
||||||
|
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||||
|
</xilinx:taxonomies>
|
||||||
|
<xilinx:displayName>gtxe2_top_v1_0</xilinx:displayName>
|
||||||
|
<xilinx:coreRevision>4</xilinx:coreRevision>
|
||||||
|
<xilinx:coreCreationDateTime>2015-04-07T08:40:29Z</xilinx:coreCreationDateTime>
|
||||||
|
<xilinx:tags>
|
||||||
|
<xilinx:tag xilinx:name="xilinx.com:user:gtxe2_top:1.0_ARCHIVE_LOCATION">C:/file_repository_2015.1/common/gtxe2_top_v1_00_a</xilinx:tag>
|
||||||
|
</xilinx:tags>
|
||||||
|
</xilinx:coreExtensions>
|
||||||
|
<xilinx:packagingInfo>
|
||||||
|
<xilinx:xilinxVersion>2015.1</xilinx:xilinxVersion>
|
||||||
|
<xilinx:checksum xilinx:scope="busInterfaces"
|
||||||
|
xilinx:value="7146aa97"/>
|
||||||
|
<xilinx:checksum xilinx:scope="fileGroups"
|
||||||
|
xilinx:value="a10f1bb1"/>
|
||||||
|
<xilinx:checksum xilinx:scope="ports"
|
||||||
|
xilinx:value="f0946559"/>
|
||||||
|
<xilinx:checksum xilinx:scope="parameters"
|
||||||
|
xilinx:value="8d5ebaa0"/>
|
||||||
|
</xilinx:packagingInfo>
|
||||||
|
</spirit:vendorExtensions>
|
||||||
|
</spirit:component>
|
||||||
|
|
@ -0,0 +1,110 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
//
|
||||||
|
// Create Date: 13:58:09 02/02/2012
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: gtxe2_top
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
module gtxe2_top(
|
||||||
|
input user_clock_p,
|
||||||
|
input user_clock_n,
|
||||||
|
output si5324_out_p,
|
||||||
|
output si5324_out_n,
|
||||||
|
input si5324_in_p,
|
||||||
|
input si5324_in_n,
|
||||||
|
output SMA_out_p,
|
||||||
|
output SMA_out_n
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
wire clk_out;
|
||||||
|
wire clock_bufg;
|
||||||
|
|
||||||
|
reg q;
|
||||||
|
|
||||||
|
IBUFDS IBUFDS_inst_user_clock(
|
||||||
|
.O(clock_out), // Buffer output
|
||||||
|
.I(user_clock_p), // Diff_p buffer input (connect directly to top-level port)
|
||||||
|
.IB(user_clock_n) // Diff_n buffer input (connect directly to top-level port)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG BUFG_inst_user_clock (
|
||||||
|
.O(clock_bufg), // 1-bit output: Clock output
|
||||||
|
.I(clock_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||||
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
||||||
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
||||||
|
) ODDR_out_clock_inst_user_clock (
|
||||||
|
.Q(clock_out_ddr), // 1-bit DDR output
|
||||||
|
.C(clock_bufg), // 1-bit clock input
|
||||||
|
.CE(1'b1), // 1-bit clock enable input
|
||||||
|
.D1(1'b1), // 1-bit data input (positive edge)
|
||||||
|
.D2(1'b0), // 1-bit data input (negative edge)
|
||||||
|
.R(), // 1-bit reset
|
||||||
|
.S() // 1-bit set
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
OBUFDS OBUFDS_inst_user_clock (
|
||||||
|
.O (si5324_out_p), // Diff_p output (connect directly to top-level port)
|
||||||
|
.OB(si5324_out_n), // Diff_n output (connect directly to top-level port)
|
||||||
|
.I (clock_out_ddr) // Buffer input
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
IBUFDS_GTE2 IBUFDS_GTE2_inst_si5324(
|
||||||
|
.O (clock_out_si5324), // Buffer output
|
||||||
|
.I (si5324_in_p), // Diff_p buffer input (connect directly to top-level port)
|
||||||
|
.IB(si5324_in_n) // Diff_n buffer input (connect directly to top-level port)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
BUFG BUFG_inst_si5324 (
|
||||||
|
.O(clock_bufg_si5324), // 1-bit output: Clock output
|
||||||
|
.I(clock_out_si5324)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
ODDR #(
|
||||||
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||||
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
||||||
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
||||||
|
) ODDR_out_clock_si5324 (
|
||||||
|
.Q(clock_out_ddr_si5324), // 1-bit DDR output
|
||||||
|
.C(clock_bufg_si5324), // 1-bit clock input
|
||||||
|
.CE(1'b1), // 1-bit clock enable input
|
||||||
|
.D1(1'b1), // 1-bit data input (positive edge)
|
||||||
|
.D2(1'b0), // 1-bit data input (negative edge)
|
||||||
|
.R(), // 1-bit reset
|
||||||
|
.S() // 1-bit set
|
||||||
|
);
|
||||||
|
|
||||||
|
OBUFDS #(
|
||||||
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
||||||
|
.SLEW("SLOW") // Specify the output slew rate
|
||||||
|
) OBUFDS_inst_si5324 (
|
||||||
|
.O (SMA_out_p), // Diff_p output (connect directly to top-level port)
|
||||||
|
.OB(SMA_out_n), // Diff_n output (connect directly to top-level port)
|
||||||
|
.I (clock_out_ddr_si5324) // Buffer input
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
version:1
|
||||||
|
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:2d31:00:00
|
||||||
|
eof:3471413770
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||||||
|
<document>
|
||||||
|
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||||
|
The structure and the elements are likely to change over the next few releases.
|
||||||
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
|
<application name="pa" timeStamp="Tue Apr 07 02:40:33 2015">
|
||||||
|
<section name="Project Information" visible="false">
|
||||||
|
<property name="ProjectID" value="49d84161241e4a138fcd9805e5baf3d4" type="ProjectID"/>
|
||||||
|
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||||
|
</section>
|
||||||
|
<section name="PlanAhead Usage" visible="true">
|
||||||
|
<item name="Project Data">
|
||||||
|
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||||
|
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||||
|
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||||
|
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||||
|
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||||
|
</item>
|
||||||
|
<item name="Java Command Handlers">
|
||||||
|
<property name="CloseProject" value="-1" type="JavaHandler"/>
|
||||||
|
</item>
|
||||||
|
<item name="Other">
|
||||||
|
<property name="GuiMode" value="812" type="GuiMode"/>
|
||||||
|
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||||
|
<property name="TclMode" value="447" type="TclMode"/>
|
||||||
|
</item>
|
||||||
|
</section>
|
||||||
|
</application>
|
||||||
|
</document>
|
||||||
|
|
@ -0,0 +1,2 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<labtools version="1" minor="0"/>
|
||||||
|
|
@ -0,0 +1,102 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2015.1.0 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Version="7" Minor="5" Path="c:/file_repository_2015.1/common/gtxe2_top_v1_00_a/tmp_edit_project.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="c7a20d10f6fd421d9a3f8da54817b4ff"/>
|
||||||
|
<Option Name="Part" Val="xc7a200tfbg676-2"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="IPRepoPath" Val="$PPRDIR/."/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="31">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/src/gtxe2_top.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/component.xml">
|
||||||
|
<FileInfo SFType="IPXACT"/>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="gtxe2_top"/>
|
||||||
|
<Option Name="TopRTLFile" Val="$PPRDIR/src/gtxe2_top.v"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="gtxe2_top"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="IES">
|
||||||
|
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="9">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
|
||||||
|
<Desc>Vivado Implementation Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,10 @@
|
||||||
|
# Definitional proc to organize widgets for parameters.
|
||||||
|
proc init_gui { IPINST } {
|
||||||
|
ipgui::add_param $IPINST -name "Component_Name"
|
||||||
|
#Adding Page
|
||||||
|
ipgui::add_page $IPINST -name "Page 0"
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,541 @@
|
||||||
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||||
|
//--------------------------------------------------------------------------------
|
||||||
|
//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
|
||||||
|
//Date : Fri Jan 26 19:13:14 2018
|
||||||
|
//Host : LAPTOP-AKMF2NBQ running 64-bit major release (build 9200)
|
||||||
|
//Command : generate_target system_wrapper.bd
|
||||||
|
//Design : system_wrapper
|
||||||
|
//Purpose : IP block netlist
|
||||||
|
//--------------------------------------------------------------------------------
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module system_wrapper
|
||||||
|
(DDR3_A14,
|
||||||
|
DDR3_A15,
|
||||||
|
DDR3_CKE1,
|
||||||
|
DDR3_CLK1_N,
|
||||||
|
DDR3_CLK1_P,
|
||||||
|
DDR3_ODT1,
|
||||||
|
DDR3_S1_B,
|
||||||
|
SI5324_IN_clk_n,
|
||||||
|
SI5324_IN_clk_p,
|
||||||
|
SI5324_OUT_clk_n,
|
||||||
|
SI5324_OUT_clk_p,
|
||||||
|
SMA_OUT_clk_n,
|
||||||
|
SMA_OUT_clk_p,
|
||||||
|
SM_FAN_PWM,
|
||||||
|
ULPI_clk,
|
||||||
|
ULPI_data_io,
|
||||||
|
ULPI_dir,
|
||||||
|
ULPI_next,
|
||||||
|
ULPI_rst,
|
||||||
|
ULPI_stop,
|
||||||
|
USER_CLOCK_IN_clk_n,
|
||||||
|
USER_CLOCK_IN_clk_p,
|
||||||
|
Vaux0_v_n,
|
||||||
|
Vaux0_v_p,
|
||||||
|
Vaux8_v_n,
|
||||||
|
Vaux8_v_p,
|
||||||
|
Vp_Vn_v_n,
|
||||||
|
Vp_Vn_v_p,
|
||||||
|
ddr3_sdram_addr,
|
||||||
|
ddr3_sdram_ba,
|
||||||
|
ddr3_sdram_cas_n,
|
||||||
|
ddr3_sdram_ck_n,
|
||||||
|
ddr3_sdram_ck_p,
|
||||||
|
ddr3_sdram_cke,
|
||||||
|
ddr3_sdram_cs_n,
|
||||||
|
ddr3_sdram_dm,
|
||||||
|
ddr3_sdram_dq,
|
||||||
|
ddr3_sdram_dqs_n,
|
||||||
|
ddr3_sdram_dqs_p,
|
||||||
|
ddr3_sdram_odt,
|
||||||
|
ddr3_sdram_ras_n,
|
||||||
|
ddr3_sdram_reset_n,
|
||||||
|
ddr3_sdram_we_n,
|
||||||
|
dip_switches_8bits_tri_i,
|
||||||
|
iic_main_scl_io,
|
||||||
|
iic_main_sda_io,
|
||||||
|
iic_mux_reset_b,
|
||||||
|
lcd_7bits_tri_o,
|
||||||
|
led_8bits_tri_o,
|
||||||
|
linear_flash_addr,
|
||||||
|
linear_flash_adv_ldn,
|
||||||
|
linear_flash_ce_n,
|
||||||
|
linear_flash_dq_io,
|
||||||
|
linear_flash_oen,
|
||||||
|
linear_flash_wen,
|
||||||
|
mdio_mdc_mdc,
|
||||||
|
mdio_mdc_mdio_io,
|
||||||
|
phy_reset_out,
|
||||||
|
push_buttons_5bits_tri_i,
|
||||||
|
reset,
|
||||||
|
rotary_switch_tri_i,
|
||||||
|
rs232_uart_rxd,
|
||||||
|
rs232_uart_txd,
|
||||||
|
sgmii_mgt_clk_clk_n,
|
||||||
|
sgmii_mgt_clk_clk_p,
|
||||||
|
sgmii_rxn,
|
||||||
|
sgmii_rxp,
|
||||||
|
sgmii_txn,
|
||||||
|
sgmii_txp,
|
||||||
|
sys_diff_clock_clk_n,
|
||||||
|
sys_diff_clock_clk_p);
|
||||||
|
output [0:0]DDR3_A14;
|
||||||
|
output [0:0]DDR3_A15;
|
||||||
|
output [0:0]DDR3_CKE1;
|
||||||
|
output [0:0]DDR3_CLK1_N;
|
||||||
|
output [0:0]DDR3_CLK1_P;
|
||||||
|
output [0:0]DDR3_ODT1;
|
||||||
|
output [0:0]DDR3_S1_B;
|
||||||
|
input SI5324_IN_clk_n;
|
||||||
|
input SI5324_IN_clk_p;
|
||||||
|
output SI5324_OUT_clk_n;
|
||||||
|
output SI5324_OUT_clk_p;
|
||||||
|
output SMA_OUT_clk_n;
|
||||||
|
output SMA_OUT_clk_p;
|
||||||
|
output [0:0]SM_FAN_PWM;
|
||||||
|
input ULPI_clk;
|
||||||
|
inout [7:0]ULPI_data_io;
|
||||||
|
input ULPI_dir;
|
||||||
|
input ULPI_next;
|
||||||
|
output ULPI_rst;
|
||||||
|
output ULPI_stop;
|
||||||
|
input USER_CLOCK_IN_clk_n;
|
||||||
|
input USER_CLOCK_IN_clk_p;
|
||||||
|
input Vaux0_v_n;
|
||||||
|
input Vaux0_v_p;
|
||||||
|
input Vaux8_v_n;
|
||||||
|
input Vaux8_v_p;
|
||||||
|
input Vp_Vn_v_n;
|
||||||
|
input Vp_Vn_v_p;
|
||||||
|
output [13:0]ddr3_sdram_addr;
|
||||||
|
output [2:0]ddr3_sdram_ba;
|
||||||
|
output ddr3_sdram_cas_n;
|
||||||
|
output [0:0]ddr3_sdram_ck_n;
|
||||||
|
output [0:0]ddr3_sdram_ck_p;
|
||||||
|
output [0:0]ddr3_sdram_cke;
|
||||||
|
output [0:0]ddr3_sdram_cs_n;
|
||||||
|
output [7:0]ddr3_sdram_dm;
|
||||||
|
inout [63:0]ddr3_sdram_dq;
|
||||||
|
inout [7:0]ddr3_sdram_dqs_n;
|
||||||
|
inout [7:0]ddr3_sdram_dqs_p;
|
||||||
|
output [0:0]ddr3_sdram_odt;
|
||||||
|
output ddr3_sdram_ras_n;
|
||||||
|
output ddr3_sdram_reset_n;
|
||||||
|
output ddr3_sdram_we_n;
|
||||||
|
input [7:0]dip_switches_8bits_tri_i;
|
||||||
|
inout iic_main_scl_io;
|
||||||
|
inout iic_main_sda_io;
|
||||||
|
output [1:0]iic_mux_reset_b;
|
||||||
|
output [6:0]lcd_7bits_tri_o;
|
||||||
|
output [7:0]led_8bits_tri_o;
|
||||||
|
output [26:1]linear_flash_addr;
|
||||||
|
output linear_flash_adv_ldn;
|
||||||
|
output linear_flash_ce_n;
|
||||||
|
inout [15:0]linear_flash_dq_io;
|
||||||
|
output linear_flash_oen;
|
||||||
|
output linear_flash_wen;
|
||||||
|
output mdio_mdc_mdc;
|
||||||
|
inout mdio_mdc_mdio_io;
|
||||||
|
output [0:0]phy_reset_out;
|
||||||
|
input [4:0]push_buttons_5bits_tri_i;
|
||||||
|
input reset;
|
||||||
|
input [2:0]rotary_switch_tri_i;
|
||||||
|
input rs232_uart_rxd;
|
||||||
|
output rs232_uart_txd;
|
||||||
|
input sgmii_mgt_clk_clk_n;
|
||||||
|
input sgmii_mgt_clk_clk_p;
|
||||||
|
input sgmii_rxn;
|
||||||
|
input sgmii_rxp;
|
||||||
|
output sgmii_txn;
|
||||||
|
output sgmii_txp;
|
||||||
|
input sys_diff_clock_clk_n;
|
||||||
|
input sys_diff_clock_clk_p;
|
||||||
|
|
||||||
|
wire [0:0]DDR3_A14;
|
||||||
|
wire [0:0]DDR3_A15;
|
||||||
|
wire [0:0]DDR3_CKE1;
|
||||||
|
wire [0:0]DDR3_CLK1_N;
|
||||||
|
wire [0:0]DDR3_CLK1_P;
|
||||||
|
wire [0:0]DDR3_ODT1;
|
||||||
|
wire [0:0]DDR3_S1_B;
|
||||||
|
wire SI5324_IN_clk_n;
|
||||||
|
wire SI5324_IN_clk_p;
|
||||||
|
wire SI5324_OUT_clk_n;
|
||||||
|
wire SI5324_OUT_clk_p;
|
||||||
|
wire SMA_OUT_clk_n;
|
||||||
|
wire SMA_OUT_clk_p;
|
||||||
|
wire [0:0]SM_FAN_PWM;
|
||||||
|
wire ULPI_clk;
|
||||||
|
wire [0:0]ULPI_data_i_0;
|
||||||
|
wire [1:1]ULPI_data_i_1;
|
||||||
|
wire [2:2]ULPI_data_i_2;
|
||||||
|
wire [3:3]ULPI_data_i_3;
|
||||||
|
wire [4:4]ULPI_data_i_4;
|
||||||
|
wire [5:5]ULPI_data_i_5;
|
||||||
|
wire [6:6]ULPI_data_i_6;
|
||||||
|
wire [7:7]ULPI_data_i_7;
|
||||||
|
wire [0:0]ULPI_data_io_0;
|
||||||
|
wire [1:1]ULPI_data_io_1;
|
||||||
|
wire [2:2]ULPI_data_io_2;
|
||||||
|
wire [3:3]ULPI_data_io_3;
|
||||||
|
wire [4:4]ULPI_data_io_4;
|
||||||
|
wire [5:5]ULPI_data_io_5;
|
||||||
|
wire [6:6]ULPI_data_io_6;
|
||||||
|
wire [7:7]ULPI_data_io_7;
|
||||||
|
wire [0:0]ULPI_data_o_0;
|
||||||
|
wire [1:1]ULPI_data_o_1;
|
||||||
|
wire [2:2]ULPI_data_o_2;
|
||||||
|
wire [3:3]ULPI_data_o_3;
|
||||||
|
wire [4:4]ULPI_data_o_4;
|
||||||
|
wire [5:5]ULPI_data_o_5;
|
||||||
|
wire [6:6]ULPI_data_o_6;
|
||||||
|
wire [7:7]ULPI_data_o_7;
|
||||||
|
wire ULPI_data_t;
|
||||||
|
wire ULPI_dir;
|
||||||
|
wire ULPI_next;
|
||||||
|
wire ULPI_rst;
|
||||||
|
wire ULPI_stop;
|
||||||
|
wire USER_CLOCK_IN_clk_n;
|
||||||
|
wire USER_CLOCK_IN_clk_p;
|
||||||
|
wire Vaux0_v_n;
|
||||||
|
wire Vaux0_v_p;
|
||||||
|
wire Vaux8_v_n;
|
||||||
|
wire Vaux8_v_p;
|
||||||
|
wire Vp_Vn_v_n;
|
||||||
|
wire Vp_Vn_v_p;
|
||||||
|
wire [13:0]ddr3_sdram_addr;
|
||||||
|
wire [2:0]ddr3_sdram_ba;
|
||||||
|
wire ddr3_sdram_cas_n;
|
||||||
|
wire [0:0]ddr3_sdram_ck_n;
|
||||||
|
wire [0:0]ddr3_sdram_ck_p;
|
||||||
|
wire [0:0]ddr3_sdram_cke;
|
||||||
|
wire [0:0]ddr3_sdram_cs_n;
|
||||||
|
wire [7:0]ddr3_sdram_dm;
|
||||||
|
wire [63:0]ddr3_sdram_dq;
|
||||||
|
wire [7:0]ddr3_sdram_dqs_n;
|
||||||
|
wire [7:0]ddr3_sdram_dqs_p;
|
||||||
|
wire [0:0]ddr3_sdram_odt;
|
||||||
|
wire ddr3_sdram_ras_n;
|
||||||
|
wire ddr3_sdram_reset_n;
|
||||||
|
wire ddr3_sdram_we_n;
|
||||||
|
wire [7:0]dip_switches_8bits_tri_i;
|
||||||
|
wire iic_main_scl_i;
|
||||||
|
wire iic_main_scl_io;
|
||||||
|
wire iic_main_scl_o;
|
||||||
|
wire iic_main_scl_t;
|
||||||
|
wire iic_main_sda_i;
|
||||||
|
wire iic_main_sda_io;
|
||||||
|
wire iic_main_sda_o;
|
||||||
|
wire iic_main_sda_t;
|
||||||
|
wire [1:0]iic_mux_reset_b;
|
||||||
|
wire [6:0]lcd_7bits_tri_o;
|
||||||
|
wire [7:0]led_8bits_tri_o;
|
||||||
|
wire [26:1]linear_flash_addr;
|
||||||
|
wire linear_flash_adv_ldn;
|
||||||
|
wire linear_flash_ce_n;
|
||||||
|
wire [0:0]linear_flash_dq_i_0;
|
||||||
|
wire [1:1]linear_flash_dq_i_1;
|
||||||
|
wire [10:10]linear_flash_dq_i_10;
|
||||||
|
wire [11:11]linear_flash_dq_i_11;
|
||||||
|
wire [12:12]linear_flash_dq_i_12;
|
||||||
|
wire [13:13]linear_flash_dq_i_13;
|
||||||
|
wire [14:14]linear_flash_dq_i_14;
|
||||||
|
wire [15:15]linear_flash_dq_i_15;
|
||||||
|
wire [2:2]linear_flash_dq_i_2;
|
||||||
|
wire [3:3]linear_flash_dq_i_3;
|
||||||
|
wire [4:4]linear_flash_dq_i_4;
|
||||||
|
wire [5:5]linear_flash_dq_i_5;
|
||||||
|
wire [6:6]linear_flash_dq_i_6;
|
||||||
|
wire [7:7]linear_flash_dq_i_7;
|
||||||
|
wire [8:8]linear_flash_dq_i_8;
|
||||||
|
wire [9:9]linear_flash_dq_i_9;
|
||||||
|
wire [0:0]linear_flash_dq_io_0;
|
||||||
|
wire [1:1]linear_flash_dq_io_1;
|
||||||
|
wire [10:10]linear_flash_dq_io_10;
|
||||||
|
wire [11:11]linear_flash_dq_io_11;
|
||||||
|
wire [12:12]linear_flash_dq_io_12;
|
||||||
|
wire [13:13]linear_flash_dq_io_13;
|
||||||
|
wire [14:14]linear_flash_dq_io_14;
|
||||||
|
wire [15:15]linear_flash_dq_io_15;
|
||||||
|
wire [2:2]linear_flash_dq_io_2;
|
||||||
|
wire [3:3]linear_flash_dq_io_3;
|
||||||
|
wire [4:4]linear_flash_dq_io_4;
|
||||||
|
wire [5:5]linear_flash_dq_io_5;
|
||||||
|
wire [6:6]linear_flash_dq_io_6;
|
||||||
|
wire [7:7]linear_flash_dq_io_7;
|
||||||
|
wire [8:8]linear_flash_dq_io_8;
|
||||||
|
wire [9:9]linear_flash_dq_io_9;
|
||||||
|
wire [0:0]linear_flash_dq_o_0;
|
||||||
|
wire [1:1]linear_flash_dq_o_1;
|
||||||
|
wire [10:10]linear_flash_dq_o_10;
|
||||||
|
wire [11:11]linear_flash_dq_o_11;
|
||||||
|
wire [12:12]linear_flash_dq_o_12;
|
||||||
|
wire [13:13]linear_flash_dq_o_13;
|
||||||
|
wire [14:14]linear_flash_dq_o_14;
|
||||||
|
wire [15:15]linear_flash_dq_o_15;
|
||||||
|
wire [2:2]linear_flash_dq_o_2;
|
||||||
|
wire [3:3]linear_flash_dq_o_3;
|
||||||
|
wire [4:4]linear_flash_dq_o_4;
|
||||||
|
wire [5:5]linear_flash_dq_o_5;
|
||||||
|
wire [6:6]linear_flash_dq_o_6;
|
||||||
|
wire [7:7]linear_flash_dq_o_7;
|
||||||
|
wire [8:8]linear_flash_dq_o_8;
|
||||||
|
wire [9:9]linear_flash_dq_o_9;
|
||||||
|
wire [0:0]linear_flash_dq_t_0;
|
||||||
|
wire [1:1]linear_flash_dq_t_1;
|
||||||
|
wire [10:10]linear_flash_dq_t_10;
|
||||||
|
wire [11:11]linear_flash_dq_t_11;
|
||||||
|
wire [12:12]linear_flash_dq_t_12;
|
||||||
|
wire [13:13]linear_flash_dq_t_13;
|
||||||
|
wire [14:14]linear_flash_dq_t_14;
|
||||||
|
wire [15:15]linear_flash_dq_t_15;
|
||||||
|
wire [2:2]linear_flash_dq_t_2;
|
||||||
|
wire [3:3]linear_flash_dq_t_3;
|
||||||
|
wire [4:4]linear_flash_dq_t_4;
|
||||||
|
wire [5:5]linear_flash_dq_t_5;
|
||||||
|
wire [6:6]linear_flash_dq_t_6;
|
||||||
|
wire [7:7]linear_flash_dq_t_7;
|
||||||
|
wire [8:8]linear_flash_dq_t_8;
|
||||||
|
wire [9:9]linear_flash_dq_t_9;
|
||||||
|
wire linear_flash_oen;
|
||||||
|
wire linear_flash_wen;
|
||||||
|
wire mdio_mdc_mdc;
|
||||||
|
wire mdio_mdc_mdio_i;
|
||||||
|
wire mdio_mdc_mdio_io;
|
||||||
|
wire mdio_mdc_mdio_o;
|
||||||
|
wire mdio_mdc_mdio_t;
|
||||||
|
wire [0:0]phy_reset_out;
|
||||||
|
wire [4:0]push_buttons_5bits_tri_i;
|
||||||
|
wire reset;
|
||||||
|
wire [2:0]rotary_switch_tri_i;
|
||||||
|
wire rs232_uart_rxd;
|
||||||
|
wire rs232_uart_txd;
|
||||||
|
wire sgmii_mgt_clk_clk_n;
|
||||||
|
wire sgmii_mgt_clk_clk_p;
|
||||||
|
wire sgmii_rxn;
|
||||||
|
wire sgmii_rxp;
|
||||||
|
wire sgmii_txn;
|
||||||
|
wire sgmii_txp;
|
||||||
|
wire sys_diff_clock_clk_n;
|
||||||
|
wire sys_diff_clock_clk_p;
|
||||||
|
|
||||||
|
IOBUF ULPI_data_iobuf_0
|
||||||
|
(.I(ULPI_data_o_0),
|
||||||
|
.IO(ULPI_data_io[0]),
|
||||||
|
.O(ULPI_data_i_0),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_1
|
||||||
|
(.I(ULPI_data_o_1),
|
||||||
|
.IO(ULPI_data_io[1]),
|
||||||
|
.O(ULPI_data_i_1),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_2
|
||||||
|
(.I(ULPI_data_o_2),
|
||||||
|
.IO(ULPI_data_io[2]),
|
||||||
|
.O(ULPI_data_i_2),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_3
|
||||||
|
(.I(ULPI_data_o_3),
|
||||||
|
.IO(ULPI_data_io[3]),
|
||||||
|
.O(ULPI_data_i_3),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_4
|
||||||
|
(.I(ULPI_data_o_4),
|
||||||
|
.IO(ULPI_data_io[4]),
|
||||||
|
.O(ULPI_data_i_4),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_5
|
||||||
|
(.I(ULPI_data_o_5),
|
||||||
|
.IO(ULPI_data_io[5]),
|
||||||
|
.O(ULPI_data_i_5),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_6
|
||||||
|
(.I(ULPI_data_o_6),
|
||||||
|
.IO(ULPI_data_io[6]),
|
||||||
|
.O(ULPI_data_i_6),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF ULPI_data_iobuf_7
|
||||||
|
(.I(ULPI_data_o_7),
|
||||||
|
.IO(ULPI_data_io[7]),
|
||||||
|
.O(ULPI_data_i_7),
|
||||||
|
.T(ULPI_data_t));
|
||||||
|
IOBUF iic_main_scl_iobuf
|
||||||
|
(.I(iic_main_scl_o),
|
||||||
|
.IO(iic_main_scl_io),
|
||||||
|
.O(iic_main_scl_i),
|
||||||
|
.T(iic_main_scl_t));
|
||||||
|
IOBUF iic_main_sda_iobuf
|
||||||
|
(.I(iic_main_sda_o),
|
||||||
|
.IO(iic_main_sda_io),
|
||||||
|
.O(iic_main_sda_i),
|
||||||
|
.T(iic_main_sda_t));
|
||||||
|
IOBUF linear_flash_dq_iobuf_0
|
||||||
|
(.I(linear_flash_dq_o_0),
|
||||||
|
.IO(linear_flash_dq_io[0]),
|
||||||
|
.O(linear_flash_dq_i_0),
|
||||||
|
.T(linear_flash_dq_t_0));
|
||||||
|
IOBUF linear_flash_dq_iobuf_1
|
||||||
|
(.I(linear_flash_dq_o_1),
|
||||||
|
.IO(linear_flash_dq_io[1]),
|
||||||
|
.O(linear_flash_dq_i_1),
|
||||||
|
.T(linear_flash_dq_t_1));
|
||||||
|
IOBUF linear_flash_dq_iobuf_10
|
||||||
|
(.I(linear_flash_dq_o_10),
|
||||||
|
.IO(linear_flash_dq_io[10]),
|
||||||
|
.O(linear_flash_dq_i_10),
|
||||||
|
.T(linear_flash_dq_t_10));
|
||||||
|
IOBUF linear_flash_dq_iobuf_11
|
||||||
|
(.I(linear_flash_dq_o_11),
|
||||||
|
.IO(linear_flash_dq_io[11]),
|
||||||
|
.O(linear_flash_dq_i_11),
|
||||||
|
.T(linear_flash_dq_t_11));
|
||||||
|
IOBUF linear_flash_dq_iobuf_12
|
||||||
|
(.I(linear_flash_dq_o_12),
|
||||||
|
.IO(linear_flash_dq_io[12]),
|
||||||
|
.O(linear_flash_dq_i_12),
|
||||||
|
.T(linear_flash_dq_t_12));
|
||||||
|
IOBUF linear_flash_dq_iobuf_13
|
||||||
|
(.I(linear_flash_dq_o_13),
|
||||||
|
.IO(linear_flash_dq_io[13]),
|
||||||
|
.O(linear_flash_dq_i_13),
|
||||||
|
.T(linear_flash_dq_t_13));
|
||||||
|
IOBUF linear_flash_dq_iobuf_14
|
||||||
|
(.I(linear_flash_dq_o_14),
|
||||||
|
.IO(linear_flash_dq_io[14]),
|
||||||
|
.O(linear_flash_dq_i_14),
|
||||||
|
.T(linear_flash_dq_t_14));
|
||||||
|
IOBUF linear_flash_dq_iobuf_15
|
||||||
|
(.I(linear_flash_dq_o_15),
|
||||||
|
.IO(linear_flash_dq_io[15]),
|
||||||
|
.O(linear_flash_dq_i_15),
|
||||||
|
.T(linear_flash_dq_t_15));
|
||||||
|
IOBUF linear_flash_dq_iobuf_2
|
||||||
|
(.I(linear_flash_dq_o_2),
|
||||||
|
.IO(linear_flash_dq_io[2]),
|
||||||
|
.O(linear_flash_dq_i_2),
|
||||||
|
.T(linear_flash_dq_t_2));
|
||||||
|
IOBUF linear_flash_dq_iobuf_3
|
||||||
|
(.I(linear_flash_dq_o_3),
|
||||||
|
.IO(linear_flash_dq_io[3]),
|
||||||
|
.O(linear_flash_dq_i_3),
|
||||||
|
.T(linear_flash_dq_t_3));
|
||||||
|
IOBUF linear_flash_dq_iobuf_4
|
||||||
|
(.I(linear_flash_dq_o_4),
|
||||||
|
.IO(linear_flash_dq_io[4]),
|
||||||
|
.O(linear_flash_dq_i_4),
|
||||||
|
.T(linear_flash_dq_t_4));
|
||||||
|
IOBUF linear_flash_dq_iobuf_5
|
||||||
|
(.I(linear_flash_dq_o_5),
|
||||||
|
.IO(linear_flash_dq_io[5]),
|
||||||
|
.O(linear_flash_dq_i_5),
|
||||||
|
.T(linear_flash_dq_t_5));
|
||||||
|
IOBUF linear_flash_dq_iobuf_6
|
||||||
|
(.I(linear_flash_dq_o_6),
|
||||||
|
.IO(linear_flash_dq_io[6]),
|
||||||
|
.O(linear_flash_dq_i_6),
|
||||||
|
.T(linear_flash_dq_t_6));
|
||||||
|
IOBUF linear_flash_dq_iobuf_7
|
||||||
|
(.I(linear_flash_dq_o_7),
|
||||||
|
.IO(linear_flash_dq_io[7]),
|
||||||
|
.O(linear_flash_dq_i_7),
|
||||||
|
.T(linear_flash_dq_t_7));
|
||||||
|
IOBUF linear_flash_dq_iobuf_8
|
||||||
|
(.I(linear_flash_dq_o_8),
|
||||||
|
.IO(linear_flash_dq_io[8]),
|
||||||
|
.O(linear_flash_dq_i_8),
|
||||||
|
.T(linear_flash_dq_t_8));
|
||||||
|
IOBUF linear_flash_dq_iobuf_9
|
||||||
|
(.I(linear_flash_dq_o_9),
|
||||||
|
.IO(linear_flash_dq_io[9]),
|
||||||
|
.O(linear_flash_dq_i_9),
|
||||||
|
.T(linear_flash_dq_t_9));
|
||||||
|
IOBUF mdio_mdc_mdio_iobuf
|
||||||
|
(.I(mdio_mdc_mdio_o),
|
||||||
|
.IO(mdio_mdc_mdio_io),
|
||||||
|
.O(mdio_mdc_mdio_i),
|
||||||
|
.T(mdio_mdc_mdio_t));
|
||||||
|
system system_i
|
||||||
|
(.DDR3_A14(DDR3_A14),
|
||||||
|
.DDR3_A15(DDR3_A15),
|
||||||
|
.DDR3_CKE1(DDR3_CKE1),
|
||||||
|
.DDR3_CLK1_N(DDR3_CLK1_N),
|
||||||
|
.DDR3_CLK1_P(DDR3_CLK1_P),
|
||||||
|
.DDR3_ODT1(DDR3_ODT1),
|
||||||
|
.DDR3_S1_B(DDR3_S1_B),
|
||||||
|
.SI5324_IN_clk_n(SI5324_IN_clk_n),
|
||||||
|
.SI5324_IN_clk_p(SI5324_IN_clk_p),
|
||||||
|
.SI5324_OUT_clk_n(SI5324_OUT_clk_n),
|
||||||
|
.SI5324_OUT_clk_p(SI5324_OUT_clk_p),
|
||||||
|
.SMA_OUT_clk_n(SMA_OUT_clk_n),
|
||||||
|
.SMA_OUT_clk_p(SMA_OUT_clk_p),
|
||||||
|
.SM_FAN_PWM(SM_FAN_PWM),
|
||||||
|
.ULPI_clk(ULPI_clk),
|
||||||
|
.ULPI_data_i({ULPI_data_i_7,ULPI_data_i_6,ULPI_data_i_5,ULPI_data_i_4,ULPI_data_i_3,ULPI_data_i_2,ULPI_data_i_1,ULPI_data_i_0}),
|
||||||
|
.ULPI_data_o({ULPI_data_o_7,ULPI_data_o_6,ULPI_data_o_5,ULPI_data_o_4,ULPI_data_o_3,ULPI_data_o_2,ULPI_data_o_1,ULPI_data_o_0}),
|
||||||
|
.ULPI_data_t(ULPI_data_t),
|
||||||
|
.ULPI_dir(ULPI_dir),
|
||||||
|
.ULPI_next(ULPI_next),
|
||||||
|
.ULPI_rst(ULPI_rst),
|
||||||
|
.ULPI_stop(ULPI_stop),
|
||||||
|
.USER_CLOCK_IN_clk_n(USER_CLOCK_IN_clk_n),
|
||||||
|
.USER_CLOCK_IN_clk_p(USER_CLOCK_IN_clk_p),
|
||||||
|
.Vaux0_v_n(Vaux0_v_n),
|
||||||
|
.Vaux0_v_p(Vaux0_v_p),
|
||||||
|
.Vaux8_v_n(Vaux8_v_n),
|
||||||
|
.Vaux8_v_p(Vaux8_v_p),
|
||||||
|
.Vp_Vn_v_n(Vp_Vn_v_n),
|
||||||
|
.Vp_Vn_v_p(Vp_Vn_v_p),
|
||||||
|
.ddr3_sdram_addr(ddr3_sdram_addr),
|
||||||
|
.ddr3_sdram_ba(ddr3_sdram_ba),
|
||||||
|
.ddr3_sdram_cas_n(ddr3_sdram_cas_n),
|
||||||
|
.ddr3_sdram_ck_n(ddr3_sdram_ck_n),
|
||||||
|
.ddr3_sdram_ck_p(ddr3_sdram_ck_p),
|
||||||
|
.ddr3_sdram_cke(ddr3_sdram_cke),
|
||||||
|
.ddr3_sdram_cs_n(ddr3_sdram_cs_n),
|
||||||
|
.ddr3_sdram_dm(ddr3_sdram_dm),
|
||||||
|
.ddr3_sdram_dq(ddr3_sdram_dq),
|
||||||
|
.ddr3_sdram_dqs_n(ddr3_sdram_dqs_n),
|
||||||
|
.ddr3_sdram_dqs_p(ddr3_sdram_dqs_p),
|
||||||
|
.ddr3_sdram_odt(ddr3_sdram_odt),
|
||||||
|
.ddr3_sdram_ras_n(ddr3_sdram_ras_n),
|
||||||
|
.ddr3_sdram_reset_n(ddr3_sdram_reset_n),
|
||||||
|
.ddr3_sdram_we_n(ddr3_sdram_we_n),
|
||||||
|
.dip_switches_8bits_tri_i(dip_switches_8bits_tri_i),
|
||||||
|
.iic_main_scl_i(iic_main_scl_i),
|
||||||
|
.iic_main_scl_o(iic_main_scl_o),
|
||||||
|
.iic_main_scl_t(iic_main_scl_t),
|
||||||
|
.iic_main_sda_i(iic_main_sda_i),
|
||||||
|
.iic_main_sda_o(iic_main_sda_o),
|
||||||
|
.iic_main_sda_t(iic_main_sda_t),
|
||||||
|
.iic_mux_reset_b(iic_mux_reset_b),
|
||||||
|
.lcd_7bits_tri_o(lcd_7bits_tri_o),
|
||||||
|
.led_8bits_tri_o(led_8bits_tri_o),
|
||||||
|
.linear_flash_addr(linear_flash_addr),
|
||||||
|
.linear_flash_adv_ldn(linear_flash_adv_ldn),
|
||||||
|
.linear_flash_ce_n(linear_flash_ce_n),
|
||||||
|
.linear_flash_dq_i({linear_flash_dq_i_15,linear_flash_dq_i_14,linear_flash_dq_i_13,linear_flash_dq_i_12,linear_flash_dq_i_11,linear_flash_dq_i_10,linear_flash_dq_i_9,linear_flash_dq_i_8,linear_flash_dq_i_7,linear_flash_dq_i_6,linear_flash_dq_i_5,linear_flash_dq_i_4,linear_flash_dq_i_3,linear_flash_dq_i_2,linear_flash_dq_i_1,linear_flash_dq_i_0}),
|
||||||
|
.linear_flash_dq_o({linear_flash_dq_o_15,linear_flash_dq_o_14,linear_flash_dq_o_13,linear_flash_dq_o_12,linear_flash_dq_o_11,linear_flash_dq_o_10,linear_flash_dq_o_9,linear_flash_dq_o_8,linear_flash_dq_o_7,linear_flash_dq_o_6,linear_flash_dq_o_5,linear_flash_dq_o_4,linear_flash_dq_o_3,linear_flash_dq_o_2,linear_flash_dq_o_1,linear_flash_dq_o_0}),
|
||||||
|
.linear_flash_dq_t({linear_flash_dq_t_15,linear_flash_dq_t_14,linear_flash_dq_t_13,linear_flash_dq_t_12,linear_flash_dq_t_11,linear_flash_dq_t_10,linear_flash_dq_t_9,linear_flash_dq_t_8,linear_flash_dq_t_7,linear_flash_dq_t_6,linear_flash_dq_t_5,linear_flash_dq_t_4,linear_flash_dq_t_3,linear_flash_dq_t_2,linear_flash_dq_t_1,linear_flash_dq_t_0}),
|
||||||
|
.linear_flash_oen(linear_flash_oen),
|
||||||
|
.linear_flash_wen(linear_flash_wen),
|
||||||
|
.mdio_mdc_mdc(mdio_mdc_mdc),
|
||||||
|
.mdio_mdc_mdio_i(mdio_mdc_mdio_i),
|
||||||
|
.mdio_mdc_mdio_o(mdio_mdc_mdio_o),
|
||||||
|
.mdio_mdc_mdio_t(mdio_mdc_mdio_t),
|
||||||
|
.phy_reset_out(phy_reset_out),
|
||||||
|
.push_buttons_5bits_tri_i(push_buttons_5bits_tri_i),
|
||||||
|
.reset(reset),
|
||||||
|
.rotary_switch_tri_i(rotary_switch_tri_i),
|
||||||
|
.rs232_uart_rxd(rs232_uart_rxd),
|
||||||
|
.rs232_uart_txd(rs232_uart_txd),
|
||||||
|
.sgmii_mgt_clk_clk_n(sgmii_mgt_clk_clk_n),
|
||||||
|
.sgmii_mgt_clk_clk_p(sgmii_mgt_clk_clk_p),
|
||||||
|
.sgmii_rxn(sgmii_rxn),
|
||||||
|
.sgmii_rxp(sgmii_rxp),
|
||||||
|
.sgmii_txn(sgmii_txn),
|
||||||
|
.sgmii_txp(sgmii_txp),
|
||||||
|
.sys_diff_clock_clk_n(sys_diff_clock_clk_n),
|
||||||
|
.sys_diff_clock_clk_p(sys_diff_clock_clk_p));
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,203 @@
|
||||||
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
|
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||||
|
<Project NoOfControllers="1" >
|
||||||
|
<ModuleName>design_1_mig_7series_1_0</ModuleName>
|
||||||
|
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||||
|
<dci_inputs>1</dci_inputs>
|
||||||
|
<Debug_En>OFF</Debug_En>
|
||||||
|
<DataDepth_En>1024</DataDepth_En>
|
||||||
|
<LowPower_En>ON</LowPower_En>
|
||||||
|
<XADC_En>Enabled</XADC_En>
|
||||||
|
<TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
|
||||||
|
<Version>1.9</Version>
|
||||||
|
<SystemClock>Differential</SystemClock>
|
||||||
|
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||||
|
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||||
|
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||||
|
<InternalVref>1</InternalVref>
|
||||||
|
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||||
|
<dci_cascade>0</dci_cascade>
|
||||||
|
<Controller number="0" >
|
||||||
|
<MemoryDevice>DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||||
|
<TimePeriod>2500</TimePeriod>
|
||||||
|
<VccAuxIO>1.8V</VccAuxIO>
|
||||||
|
<PHYRatio>4:1</PHYRatio>
|
||||||
|
<InputClkFreq>200</InputClkFreq>
|
||||||
|
<UIExtraClocks>0</UIExtraClocks>
|
||||||
|
<MMCMClkOut0>1</MMCMClkOut0>
|
||||||
|
<MMCMClkOut1>1</MMCMClkOut1>
|
||||||
|
<MMCMClkOut2>1</MMCMClkOut2>
|
||||||
|
<MMCMClkOut3>1</MMCMClkOut3>
|
||||||
|
<MMCMClkOut4>1</MMCMClkOut4>
|
||||||
|
<DataWidth>64</DataWidth>
|
||||||
|
<DeepMemory>1</DeepMemory>
|
||||||
|
<DataMask>1</DataMask>
|
||||||
|
<ECC>Disabled</ECC>
|
||||||
|
<Ordering>Normal</Ordering>
|
||||||
|
<CustomPart>FALSE</CustomPart>
|
||||||
|
<NewPartName></NewPartName>
|
||||||
|
<RowAddress>14</RowAddress>
|
||||||
|
<ColAddress>10</ColAddress>
|
||||||
|
<BankAddress>3</BankAddress>
|
||||||
|
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||||
|
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
|
||||||
|
<PinSelection>
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A20" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B21" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B17" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A15" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A21" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B19" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C20" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A19" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A17" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A16" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D20" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C18" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D17" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C19" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D21" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C21" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D18" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K17" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K19" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J17" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="M13" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K15" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F12" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A14" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C23" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D25" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C31" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F31" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H20" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E20" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F20" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="DONTCARE" IOSTANDARD="DIFF_SSTL15" PADName="E18" SLEW="" name="sys_clk_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="DONTCARE" IOSTANDARD="DIFF_SSTL15" PADName="E19" SLEW="" name="sys_clk_p" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="DONTCARE" IOSTANDARD="LVCMOS18" PADName="AV40" SLEW="" name="sys_rst" IN_TERM="" />
|
||||||
|
</PinSelection>
|
||||||
|
<System_Clock>
|
||||||
|
<Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
|
||||||
|
</System_Clock>
|
||||||
|
<System_Control>
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||||
|
</System_Control>
|
||||||
|
<TimingParameters>
|
||||||
|
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
|
||||||
|
</TimingParameters>
|
||||||
|
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||||
|
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||||
|
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
|
||||||
|
<mrMode name="Mode" >Normal</mrMode>
|
||||||
|
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||||
|
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||||
|
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||||
|
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
|
||||||
|
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||||
|
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||||
|
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
|
||||||
|
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||||
|
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||||
|
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||||
|
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||||
|
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||||
|
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
|
||||||
|
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||||
|
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||||
|
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||||
|
<PortInterface>AXI</PortInterface>
|
||||||
|
<AXIParameters>
|
||||||
|
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||||
|
<C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
|
||||||
|
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||||
|
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
|
||||||
|
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||||
|
</AXIParameters>
|
||||||
|
</Controller>
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,203 @@
|
||||||
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
|
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||||
|
<Project NoOfControllers="1" >
|
||||||
|
<ModuleName>system_mig_7series_0_0</ModuleName>
|
||||||
|
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||||
|
<dci_inputs>1</dci_inputs>
|
||||||
|
<Debug_En>OFF</Debug_En>
|
||||||
|
<DataDepth_En>1024</DataDepth_En>
|
||||||
|
<LowPower_En>ON</LowPower_En>
|
||||||
|
<XADC_En>Disabled</XADC_En>
|
||||||
|
<TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
|
||||||
|
<Version>2.3</Version>
|
||||||
|
<SystemClock>Differential</SystemClock>
|
||||||
|
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||||
|
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||||
|
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||||
|
<InternalVref>0</InternalVref>
|
||||||
|
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||||
|
<dci_cascade>0</dci_cascade>
|
||||||
|
<Controller number="0" >
|
||||||
|
<MemoryDevice>DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||||
|
<TimePeriod>1250</TimePeriod>
|
||||||
|
<VccAuxIO>2.0V</VccAuxIO>
|
||||||
|
<PHYRatio>4:1</PHYRatio>
|
||||||
|
<InputClkFreq>200</InputClkFreq>
|
||||||
|
<UIExtraClocks>1</UIExtraClocks>
|
||||||
|
<MMCM_VCO>800</MMCM_VCO>
|
||||||
|
<MMCMClkOut0> 8.000</MMCMClkOut0>
|
||||||
|
<MMCMClkOut1>1</MMCMClkOut1>
|
||||||
|
<MMCMClkOut2>1</MMCMClkOut2>
|
||||||
|
<MMCMClkOut3>1</MMCMClkOut3>
|
||||||
|
<MMCMClkOut4>1</MMCMClkOut4>
|
||||||
|
<DataWidth>64</DataWidth>
|
||||||
|
<DeepMemory>1</DeepMemory>
|
||||||
|
<DataMask>1</DataMask>
|
||||||
|
<ECC>Disabled</ECC>
|
||||||
|
<Ordering>Normal</Ordering>
|
||||||
|
<CustomPart>FALSE</CustomPart>
|
||||||
|
<NewPartName></NewPartName>
|
||||||
|
<RowAddress>14</RowAddress>
|
||||||
|
<ColAddress>10</ColAddress>
|
||||||
|
<BankAddress>3</BankAddress>
|
||||||
|
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||||
|
<C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
|
||||||
|
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
|
||||||
|
<PinSelection>
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="" name="ddr3_cas_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_ras_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="" name="ddr3_reset_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_we_n" IN_TERM="" />
|
||||||
|
</PinSelection>
|
||||||
|
<System_Clock>
|
||||||
|
<Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
|
||||||
|
</System_Clock>
|
||||||
|
<System_Control>
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||||
|
</System_Control>
|
||||||
|
<TimingParameters>
|
||||||
|
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
|
||||||
|
</TimingParameters>
|
||||||
|
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||||
|
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||||
|
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
|
||||||
|
<mrMode name="Mode" >Normal</mrMode>
|
||||||
|
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||||
|
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||||
|
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||||
|
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
|
||||||
|
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||||
|
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||||
|
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
|
||||||
|
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||||
|
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||||
|
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||||
|
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||||
|
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||||
|
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
|
||||||
|
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||||
|
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||||
|
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||||
|
<PortInterface>AXI</PortInterface>
|
||||||
|
<AXIParameters>
|
||||||
|
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||||
|
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||||
|
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||||
|
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
|
||||||
|
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||||
|
</AXIParameters>
|
||||||
|
</Controller>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,203 @@
|
||||||
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
|
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||||
|
<Project NoOfControllers="1" >
|
||||||
|
<ModuleName>system_mig_7series_0_0</ModuleName>
|
||||||
|
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||||
|
<dci_inputs>1</dci_inputs>
|
||||||
|
<Debug_En>OFF</Debug_En>
|
||||||
|
<DataDepth_En>1024</DataDepth_En>
|
||||||
|
<LowPower_En>ON</LowPower_En>
|
||||||
|
<XADC_En>Disabled</XADC_En>
|
||||||
|
<TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
|
||||||
|
<Version>2.3</Version>
|
||||||
|
<SystemClock>Differential</SystemClock>
|
||||||
|
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||||
|
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||||
|
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||||
|
<InternalVref>0</InternalVref>
|
||||||
|
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||||
|
<dci_cascade>0</dci_cascade>
|
||||||
|
<Controller number="0" >
|
||||||
|
<MemoryDevice>DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||||
|
<TimePeriod>1250</TimePeriod>
|
||||||
|
<VccAuxIO>2.0V</VccAuxIO>
|
||||||
|
<PHYRatio>4:1</PHYRatio>
|
||||||
|
<InputClkFreq>200</InputClkFreq>
|
||||||
|
<UIExtraClocks>1</UIExtraClocks>
|
||||||
|
<MMCM_VCO>800</MMCM_VCO>
|
||||||
|
<MMCMClkOut0> 8.000</MMCMClkOut0>
|
||||||
|
<MMCMClkOut1>1</MMCMClkOut1>
|
||||||
|
<MMCMClkOut2>1</MMCMClkOut2>
|
||||||
|
<MMCMClkOut3>1</MMCMClkOut3>
|
||||||
|
<MMCMClkOut4>1</MMCMClkOut4>
|
||||||
|
<DataWidth>64</DataWidth>
|
||||||
|
<DeepMemory>1</DeepMemory>
|
||||||
|
<DataMask>1</DataMask>
|
||||||
|
<ECC>Disabled</ECC>
|
||||||
|
<Ordering>Normal</Ordering>
|
||||||
|
<CustomPart>FALSE</CustomPart>
|
||||||
|
<NewPartName></NewPartName>
|
||||||
|
<RowAddress>14</RowAddress>
|
||||||
|
<ColAddress>10</ColAddress>
|
||||||
|
<BankAddress>3</BankAddress>
|
||||||
|
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||||
|
<C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
|
||||||
|
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
|
||||||
|
<PinSelection>
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="" name="ddr3_cas_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_ras_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="" name="ddr3_reset_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_we_n" IN_TERM="" />
|
||||||
|
</PinSelection>
|
||||||
|
<System_Clock>
|
||||||
|
<Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
|
||||||
|
</System_Clock>
|
||||||
|
<System_Control>
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||||
|
</System_Control>
|
||||||
|
<TimingParameters>
|
||||||
|
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
|
||||||
|
</TimingParameters>
|
||||||
|
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||||
|
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||||
|
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
|
||||||
|
<mrMode name="Mode" >Normal</mrMode>
|
||||||
|
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||||
|
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||||
|
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||||
|
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
|
||||||
|
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||||
|
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||||
|
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
|
||||||
|
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||||
|
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||||
|
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||||
|
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||||
|
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||||
|
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
|
||||||
|
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||||
|
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||||
|
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||||
|
<PortInterface>AXI</PortInterface>
|
||||||
|
<AXIParameters>
|
||||||
|
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||||
|
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||||
|
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||||
|
<C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
|
||||||
|
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||||
|
</AXIParameters>
|
||||||
|
</Controller>
|
||||||
|
|
||||||
|
</Project>
|
||||||
Loading…
Reference in New Issue