From 6b13247811d1eb86639f365f7ac5b1d5e2be4d90 Mon Sep 17 00:00:00 2001 From: Mark Coldebella Date: Tue, 6 Feb 2018 21:12:12 -0600 Subject: [PATCH] Initial import of BIST build, to share --- ProjectVC/project_01/README.txt | 16 + ProjectVC/project_01/bist_sha256.tcl | 1521 +++++++++++++++++ .../project_01/sources/constrs/system.xdc | 100 ++ .../sources/gtxe2_top_v1_00_a/component.xml | 354 ++++ .../sources/gtxe2_top_v1_00_a/src/gtxe2_top.v | 110 ++ .../wt/java_command_handlers.wdf | 3 + .../tmp_edit_project.cache/wt/webtalk_pa.xml | 29 + .../tmp_edit_project.hw/tmp_edit_project.lpr | 2 + .../gtxe2_top_v1_00_a/tmp_edit_project.xpr | 102 ++ .../gtxe2_top_v1_00_a/xgui/gtxe2_top_v1_0.tcl | 10 + .../project_01/sources/hdl/system_wrapper.v | 541 ++++++ .../ip/system_mig_7series_0_0/board.prj | 203 +++ .../ip/system_mig_7series_0_0/mig_a.prj | 203 +++ .../ip/system_mig_7series_0_0/mig_b.prj | 203 +++ 14 files changed, 3397 insertions(+) create mode 100644 ProjectVC/project_01/README.txt create mode 100644 ProjectVC/project_01/bist_sha256.tcl create mode 100644 ProjectVC/project_01/sources/constrs/system.xdc create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/component.xml create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/src/gtxe2_top.v create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/java_command_handlers.wdf create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/webtalk_pa.xml create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.hw/tmp_edit_project.lpr create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.xpr create mode 100644 ProjectVC/project_01/sources/gtxe2_top_v1_00_a/xgui/gtxe2_top_v1_0.tcl create mode 100644 ProjectVC/project_01/sources/hdl/system_wrapper.v create mode 100644 ProjectVC/project_01/sources/ip/system_mig_7series_0_0/board.prj create mode 100644 ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_a.prj create mode 100644 ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_b.prj diff --git a/ProjectVC/project_01/README.txt b/ProjectVC/project_01/README.txt new file mode 100644 index 0000000..5a9062f --- /dev/null +++ b/ProjectVC/project_01/README.txt @@ -0,0 +1,16 @@ +This project is compiled with the following Vivado version + +Vivado v2017.4 (64-bit) +SW Build: 2086221 on Fri Dec 15 20:55:39 MST 2017 +IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017 + +It uses two Xilinx IP modules that require temporary hardware licenses +axi_ethernet_0 AXI 1G/2.5G Ethernet Subsystem:7.1 +axi_usb2_device_0 AXI USB2 Device:5.0 + +From the command line +Go to the directory this file is in +Type vivado -mode tcl +At the vivado prompt +Type source bist_sha256.tcl +The project will be built in the bist_sha256 directory \ No newline at end of file diff --git a/ProjectVC/project_01/bist_sha256.tcl b/ProjectVC/project_01/bist_sha256.tcl new file mode 100644 index 0000000..35424d1 --- /dev/null +++ b/ProjectVC/project_01/bist_sha256.tcl @@ -0,0 +1,1521 @@ +#***************************************************************************************** +# Vivado (TM) v2017.4 (64-bit) +# +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (rebuild_bist.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "C:/Project/bist_two/bist_two.srcs/sources_1/bd/system/hdl/system_wrapper.v" +# "C:/Project/bist_two/bist_two.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/board.prj" +# "C:/Project/bist_two/bist_two.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/mig_a.prj" +# "C:/Project/bist_two/bist_two.srcs/sources_1/bd/system/ip/system_mig_7series_0_0/mig_b.prj" +# "C:/Project/bist_two/bist_two.sdk/hello_usb2/Debug/hello_usb2.elf" +# "C:/Project/bist_two/bist_two.sdk/lwip_echo_server/Debug/lwip_echo_server.elf" +# "C:/Project/bist_two/bist_two.sdk/bist_app/Debug/bist_app.elf" +# "C:/Project/bist_two/bist_two.srcs/constrs_1/imports/vc707_bist/system.xdc" +# +# 3. The following remote source files that were added to the original project:- +# +# +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set project_name "bist_sha256" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set project_name $::user_project_name +} + +variable script_file +set script_file "bist_sha256.tcl" + +# Create project +create_project ${project_name} ./${project_name} -force -part xc7vx485tffg1761-2 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +# None + +# Set project properties +set obj [current_project] +set_property -name "board_connections" -value "" -objects $obj +set_property -name "board_part" -value "xilinx.com:vc707:part0:1.2" -objects $obj +set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj +set_property -name "compxlib.funcsim" -value "1" -objects $obj +set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj +set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/modelsim" -objects $obj +set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj +set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/questa" -objects $obj +set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/riviera" -objects $obj +set_property -name "compxlib.timesim" -value "1" -objects $obj +set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/vcs" -objects $obj +set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj +set_property -name "corecontainer.enable" -value "0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.rom.debug_type" -value "0" -objects $obj +set_property -name "dsa.rom.prom_type" -value "0" -objects $obj +set_property -name "enable_optional_runs_sta" -value "0" -objects $obj +set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_interface_inference_priority" -value "" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj +set_property -name "project_type" -value "Default" -objects $obj +set_property -name "pr_flow" -value "0" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "source_mgmt_mode" -value "All" -objects $obj +set_property -name "target_language" -value "Verilog" -objects $obj +set_property -name "target_simulator" -value "XSim" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj +set_property -name "xsim.array_display_limit" -value "1024" -objects $obj +set_property -name "xsim.radix" -value "hex" -objects $obj +set_property -name "xsim.time_unit" -value "ns" -objects $obj +set_property -name "xsim.trace_limit" -value "65536" -objects $obj + +#add_files [ glob ./btc_dsha256/trunk/rtl/vhdl/misc/*.vhd ] +#add_files [ glob ./sources/hdl/*.v ] +#add_files -fileset sim_1 [ glob ./sources/ip/system_mig_7series_0_0/*.prj ] +#import_files -force -norecurse + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/sources/gtxe2_top_v1_00_a"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + "[file normalize "$origin_dir/sources/hdl/system_wrapper.v"]"\ + "[file normalize "$origin_dir/sources/ip/system_mig_7series_0_0/board.prj"]"\ + "[file normalize "$origin_dir/sources/ip/system_mig_7series_0_0/mig_a.prj"]"\ + "[file normalize "$origin_dir/sources/ip/system_mig_7series_0_0/mig_b.prj"]"\ + ] + +# "[file normalize "$origin_dir/../../../Project/bist_two/bist_two.sdk/hello_usb2/Debug/hello_usb2.elf"]"\ +#"[file normalize "$origin_dir/../../../Project/bist_two/bist_two.sdk/lwip_echo_server/Debug/lwip_echo_server.elf"]"\ +#"[file normalize "$origin_dir/../../../Project/bist_two/bist_two.sdk/bist_app/Debug/bist_app.elf"]"\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for local files +set file "hdl/system_wrapper.v" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "Verilog" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_simulation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +set file "system_mig_7series_0_0/board.prj" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +set file "system_mig_7series_0_0/mig_a.prj" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +set file "system_mig_7series_0_0/mig_b.prj" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "scoped_to_cells" -value "system_mig_7series_0_0" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "design_mode" -value "RTL" -objects $obj +set_property -name "edif_extra_search_paths" -value "" -objects $obj +set_property -name "elab_link_dcps" -value "1" -objects $obj +set_property -name "elab_load_timing_constraints" -value "1" -objects $obj +set_property -name "generic" -value "" -objects $obj +set_property -name "include_dirs" -value "" -objects $obj +set_property -name "lib_map_file" -value "" -objects $obj +set_property -name "loop_count" -value "1000" -objects $obj +set_property -name "name" -value "sources_1" -objects $obj +set_property -name "top" -value "system_wrapper" -objects $obj +set_property -name "verilog_define" -value "" -objects $obj +set_property -name "verilog_uppercase" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/sources/constrs/system.xdc"]" +puts $file +set file_imported [import_files -fileset constrs_1 $file] +puts $file_imported +set file "constrs/system.xdc" +#set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "$file_imported"]] +puts $file_obj +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "processing_order" -value "NORMAL" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "scoped_to_ref" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "name" -value "constrs_1" -objects $obj +set_property -name "target_constrs_file" -value "$proj_dir/$project_name.srcs/constrs_1/imports/constrs/system.xdc" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Adding sources referenced in BDs, if not already added + +proc cr_bd_system { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name system + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:axi_bram_ctrl:4.0\ + xilinx.com:ip:blk_mem_gen:8.4\ + xilinx.com:ip:axi_emc:3.0\ + xilinx.com:ip:axi_ethernet:7.1\ + xilinx.com:ip:axi_dma:7.1\ + xilinx.com:ip:clk_wiz:5.4\ + xilinx.com:ip:axi_gpio:2.0\ + xilinx.com:ip:axi_iic:2.0\ + xilinx.com:ip:axi_timer:2.0\ + xilinx.com:ip:axi_uart16550:2.0\ + xilinx.com:ip:axi_usb2_device:5.0\ + xilinx.com:user:gtxe2_top:1.0\ + xilinx.com:ip:mdm:3.2\ + xilinx.com:ip:microblaze:10.0\ + xilinx.com:ip:axi_intc:4.1\ + xilinx.com:ip:xlconcat:2.1\ + xilinx.com:ip:mig_7series:4.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:xadc_wiz:3.3\ + xilinx.com:ip:xlconstant:1.1\ + xilinx.com:ip:lmb_bram_if_cntlr:4.0\ + xilinx.com:ip:lmb_v10:3.0\ + " + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + +################################################################## +# MIG PRJ FILE TCL PROCs +################################################################## + +proc write_mig_file_system_mig_7series_0_0 { str_mig_prj_filepath } { + + file mkdir [ file dirname "$str_mig_prj_filepath" ] + set mig_prj_file [open $str_mig_prj_filepath w+] + + puts $mig_prj_file {} + puts $mig_prj_file {} + puts $mig_prj_file {} + puts $mig_prj_file { system_mig_7series_0_0} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { OFF} + puts $mig_prj_file { 1024} + puts $mig_prj_file { ON} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { xc7vx485t-ffg1761/-2} + puts $mig_prj_file { 2.3} + puts $mig_prj_file { Differential} + puts $mig_prj_file { Use System Clock} + puts $mig_prj_file { ACTIVE HIGH} + puts $mig_prj_file { FALSE} + puts $mig_prj_file { 0} + puts $mig_prj_file { 50 Ohms} + puts $mig_prj_file { 0} + puts $mig_prj_file { } + puts $mig_prj_file { DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6} + puts $mig_prj_file { 1250} + puts $mig_prj_file { 2.0V} + puts $mig_prj_file { 4:1} + puts $mig_prj_file { 200} + puts $mig_prj_file { 1} + puts $mig_prj_file { 800} + puts $mig_prj_file { 8.000} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 64} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { Normal} + puts $mig_prj_file { FALSE} + puts $mig_prj_file { } + puts $mig_prj_file { 14} + puts $mig_prj_file { 10} + puts $mig_prj_file { 3} + puts $mig_prj_file { 1.5V} + puts $mig_prj_file { 1073741824} + puts $mig_prj_file { ROW_BANK_COLUMN} + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { 8 - Fixed} + puts $mig_prj_file { Sequential} + puts $mig_prj_file { 11} + puts $mig_prj_file { Normal} + puts $mig_prj_file { No} + puts $mig_prj_file { Slow Exit} + puts $mig_prj_file { Enable} + puts $mig_prj_file { RZQ/7} + puts $mig_prj_file { Disable} + puts $mig_prj_file { Enable} + puts $mig_prj_file { RZQ/6} + puts $mig_prj_file { 0} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { Output Buffer Enabled} + puts $mig_prj_file { Full Array} + puts $mig_prj_file { 8} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { Normal} + puts $mig_prj_file { Dynamic ODT off} + puts $mig_prj_file { AXI} + puts $mig_prj_file { } + puts $mig_prj_file { RD_PRI_REG} + puts $mig_prj_file { 30} + puts $mig_prj_file { 512} + puts $mig_prj_file { 3} + puts $mig_prj_file { 0} + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file {} + + close $mig_prj_file +} +# End of write_mig_file_system_mig_7series_0_0() + + + + +# Hierarchical cell: microblaze_0_local_memory +proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB + + # Create pins + create_bd_pin -dir I -type clk LMB_Clk + create_bd_pin -dir I -from 0 -to 0 -type rst SYS_Rst + + # Create instance: dlmb_bram_if_cntlr, and set properties + set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $dlmb_bram_if_cntlr + + # Create instance: dlmb_v10, and set properties + set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] + + # Create instance: ilmb_bram_if_cntlr, and set properties + set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $ilmb_bram_if_cntlr + + # Create instance: ilmb_v10, and set properties + set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] + + # Create instance: lmb_bram, and set properties + set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] + set_property -dict [ list \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $lmb_bram + + # Create interface connections + connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] + + # Create port connections + connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set SI5324_IN [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 SI5324_IN ] + set SI5324_OUT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_clock_rtl:1.0 SI5324_OUT ] + set SMA_OUT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_clock_rtl:1.0 SMA_OUT ] + set ULPI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:ulpi_rtl:1.0 ULPI ] + set USER_CLOCK_IN [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 USER_CLOCK_IN ] + set Vaux0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ] + set Vaux8 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 ] + set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ] + set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] + set dip_switches_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 dip_switches_8bits ] + set iic_main [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main ] + set lcd_7bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 lcd_7bits ] + set led_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_8bits ] + set linear_flash [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 linear_flash ] + set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] + set push_buttons_5bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 push_buttons_5bits ] + set rotary_switch [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rotary_switch ] + set rs232_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart ] + set sgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii ] + set sgmii_mgt_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_mgt_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {125000000} \ + ] $sgmii_mgt_clk + set sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $sys_diff_clock + + # Create ports + set DDR3_A14 [ create_bd_port -dir O -from 0 -to 0 DDR3_A14 ] + set DDR3_A15 [ create_bd_port -dir O -from 0 -to 0 DDR3_A15 ] + set DDR3_CKE1 [ create_bd_port -dir O -from 0 -to 0 DDR3_CKE1 ] + set DDR3_CLK1_N [ create_bd_port -dir O -from 0 -to 0 DDR3_CLK1_N ] + set DDR3_CLK1_P [ create_bd_port -dir O -from 0 -to 0 DDR3_CLK1_P ] + set DDR3_ODT1 [ create_bd_port -dir O -from 0 -to 0 DDR3_ODT1 ] + set DDR3_S1_B [ create_bd_port -dir O -from 0 -to 0 DDR3_S1_B ] + set SM_FAN_PWM [ create_bd_port -dir O -from 0 -to 0 SM_FAN_PWM ] + set iic_mux_reset_b [ create_bd_port -dir O -from 1 -to 0 iic_mux_reset_b ] + set phy_reset_out [ create_bd_port -dir O -from 0 -to 0 -type rst phy_reset_out ] + set reset [ create_bd_port -dir I -type rst reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_0 ] + + # Create instance: axi_bram_ctrl_0_bram, and set properties + set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + set_property -dict [ list \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Use_RSTB_Pin {true} \ + ] $axi_bram_ctrl_0_bram + + # Create instance: axi_emc_0, and set properties + set axi_emc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_emc_0 ] + set_property -dict [ list \ + CONFIG.C_MEM0_TYPE {2} \ + CONFIG.C_TAVDV_PS_MEM_0 {130000} \ + CONFIG.C_TCEDV_PS_MEM_0 {130000} \ + CONFIG.C_THZCE_PS_MEM_0 {35000} \ + CONFIG.C_TLZWE_PS_MEM_0 {35000} \ + CONFIG.C_TPACC_PS_FLASH_0 {25000} \ + CONFIG.C_TWC_PS_MEM_0 {13000} \ + CONFIG.C_TWPH_PS_MEM_0 {12000} \ + CONFIG.C_TWP_PS_MEM_0 {70000} \ + CONFIG.C_WR_REC_TIME_MEM_0 {100000} \ + CONFIG.EMC_BOARD_INTERFACE {linear_flash} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_emc_0 + + # Create instance: axi_ethernet_0, and set properties + set axi_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.1 axi_ethernet_0 ] + set_property -dict [ list \ + CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_mgt_clk} \ + CONFIG.ETHERNET_BOARD_INTERFACE {sgmii} \ + CONFIG.Frame_Filter {false} \ + CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \ + CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out} \ + CONFIG.PHY_TYPE {SGMII} \ + CONFIG.RXMEM {32k} \ + CONFIG.Statistics_Counters {false} \ + CONFIG.TXMEM {32k} \ + ] $axi_ethernet_0 + + # Create instance: axi_ethernet_0_dma, and set properties + set axi_ethernet_0_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_0_dma ] + set_property -dict [ list \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_sg_length_width {16} \ + CONFIG.c_sg_use_stsapp_length {1} \ + ] $axi_ethernet_0_dma + + # Create instance: axi_ethernet_0_refclk, and set properties + set axi_ethernet_0_refclk [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 axi_ethernet_0_refclk ] + set_property -dict [ list \ + CONFIG.CLKOUT1_JITTER {114.829} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200} \ + CONFIG.MMCM_CLKIN1_PERIOD {10.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \ + CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \ + CONFIG.USE_LOCKED {false} \ + CONFIG.USE_RESET {false} \ + ] $axi_ethernet_0_refclk + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.GPIO_BOARD_INTERFACE {dip_switches_8bits} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_0 + + # Create instance: axi_gpio_1, and set properties + set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + set_property -dict [ list \ + CONFIG.GPIO_BOARD_INTERFACE {lcd_7bits} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_1 + + # Create instance: axi_gpio_2, and set properties + set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + set_property -dict [ list \ + CONFIG.GPIO_BOARD_INTERFACE {led_8bits} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_2 + + # Create instance: axi_gpio_3, and set properties + set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ] + set_property -dict [ list \ + CONFIG.GPIO_BOARD_INTERFACE {push_buttons_5bits} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_3 + + # Create instance: axi_gpio_4, and set properties + set axi_gpio_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_4 ] + set_property -dict [ list \ + CONFIG.GPIO_BOARD_INTERFACE {rotary_switch} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_4 + + # Create instance: axi_iic_0, and set properties + set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] + set_property -dict [ list \ + CONFIG.C_DEFAULT_VALUE {0xFF} \ + CONFIG.C_GPO_WIDTH {2} \ + CONFIG.C_SCL_INERTIAL_DELAY {5} \ + CONFIG.C_SDA_INERTIAL_DELAY {5} \ + CONFIG.IIC_BOARD_INTERFACE {iic_main} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_iic_0 + + # Create instance: axi_mem_intercon, and set properties + set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] + set_property -dict [ list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {5} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $axi_mem_intercon + + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + + # Create instance: axi_uart16550_0, and set properties + set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] + set_property -dict [ list \ + CONFIG.UART_BOARD_INTERFACE {rs232_uart} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_uart16550_0 + + # Create instance: axi_usb2_device_0, and set properties + set axi_usb2_device_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_usb2_device:5.0 axi_usb2_device_0 ] + + # Create instance: gtxe2_top_0, and set properties + set gtxe2_top_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:gtxe2_top:1.0 gtxe2_top_0 ] + + # Create instance: mdm_1, and set properties + set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] + set_property -dict [ list \ + CONFIG.C_USE_UART {1} \ + ] $mdm_1 + + # Create instance: microblaze_0, and set properties + set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ] + set_property -dict [ list \ + CONFIG.C_CACHE_BYTE_SIZE {8192} \ + CONFIG.C_DCACHE_BASEADDR {0x0000000080000000} \ + CONFIG.C_DCACHE_BYTE_SIZE {8192} \ + CONFIG.C_DCACHE_HIGHADDR {0x00000000FFFFFFFF} \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_D_LMB {1} \ + CONFIG.C_ICACHE_BASEADDR {0x0000000080000000} \ + CONFIG.C_ICACHE_HIGHADDR {0x00000000FFFFFFFF} \ + CONFIG.C_I_LMB {1} \ + CONFIG.C_USE_DCACHE {1} \ + CONFIG.C_USE_ICACHE {1} \ + ] $microblaze_0 + + # Create instance: microblaze_0_axi_intc, and set properties + set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ] + set_property -dict [ list \ + CONFIG.C_HAS_FAST {1} \ + ] $microblaze_0_axi_intc + + # Create instance: microblaze_0_axi_periph, and set properties + set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {15} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $microblaze_0_axi_periph + + # Create instance: microblaze_0_local_memory + create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory + + # Create instance: microblaze_0_xlconcat, and set properties + set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {9} \ + ] $microblaze_0_xlconcat + + # Create instance: mig_7series_0, and set properties + set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 mig_7series_0 ] + + # Generate the PRJ File for MIG + set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ] + set str_mig_file_name mig_b.prj + set str_mig_file_path ${str_mig_folder}/${str_mig_file_name} + + write_mig_file_system_mig_7series_0_0 $str_mig_file_path + + set_property -dict [ list \ + CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.XML_INPUT_FILE {mig_b.prj} \ + ] $mig_7series_0 + + # Create instance: rst_mig_7series_0_100M, and set properties + set rst_mig_7series_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_mig_7series_0_100M ] + + # Create instance: rst_mig_7series_0_200M, and set properties + set rst_mig_7series_0_200M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_mig_7series_0_200M ] + + # Create instance: xadc_wiz_0, and set properties + set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ] + set_property -dict [ list \ + CONFIG.CHANNEL_ENABLE_TEMPERATURE {true} \ + CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} \ + CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} \ + CONFIG.CHANNEL_ENABLE_VP_VN {true} \ + CONFIG.ENABLE_RESET {false} \ + CONFIG.ENABLE_TEMP_BUS {true} \ + CONFIG.INTERFACE_SELECTION {Enable_AXI} \ + CONFIG.SEQUENCER_MODE {Off} \ + CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} \ + ] $xadc_wiz_0 + + set_property -dict [ list \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + ] [get_bd_intf_pins /xadc_wiz_0/s_axi_lite] + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + + # Create interface connections + connect_bd_intf_net -intf_net SI5324_IN_1 [get_bd_intf_ports SI5324_IN] [get_bd_intf_pins gtxe2_top_0/SI5324_IN] + connect_bd_intf_net -intf_net ULPI_1 [get_bd_intf_ports ULPI] [get_bd_intf_pins axi_usb2_device_0/ULPI] + connect_bd_intf_net -intf_net USER_CLOCK_IN_1 [get_bd_intf_ports USER_CLOCK_IN] [get_bd_intf_pins gtxe2_top_0/USER_CLOCK_IN] + connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_ports Vaux0] [get_bd_intf_pins xadc_wiz_0/Vaux0] + connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_ports Vaux8] [get_bd_intf_pins xadc_wiz_0/Vaux8] + connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_ports Vp_Vn] [get_bd_intf_pins xadc_wiz_0/Vp_Vn] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB] + connect_bd_intf_net -intf_net axi_emc_0_EMC_INTF [get_bd_intf_ports linear_flash] [get_bd_intf_pins axi_emc_0/EMC_INTF] + connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXIS_CNTRL [get_bd_intf_pins axi_ethernet_0/s_axis_txc] [get_bd_intf_pins axi_ethernet_0_dma/M_AXIS_CNTRL] + connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXIS_MM2S [get_bd_intf_pins axi_ethernet_0/s_axis_txd] [get_bd_intf_pins axi_ethernet_0_dma/M_AXIS_MM2S] + connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXI_MM2S [get_bd_intf_pins axi_ethernet_0_dma/M_AXI_MM2S] [get_bd_intf_pins axi_mem_intercon/S03_AXI] + connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXI_S2MM [get_bd_intf_pins axi_ethernet_0_dma/M_AXI_S2MM] [get_bd_intf_pins axi_mem_intercon/S04_AXI] + connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXI_SG [get_bd_intf_pins axi_ethernet_0_dma/M_AXI_SG] [get_bd_intf_pins axi_mem_intercon/S02_AXI] + connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxd [get_bd_intf_pins axi_ethernet_0/m_axis_rxd] [get_bd_intf_pins axi_ethernet_0_dma/S_AXIS_S2MM] + connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxs [get_bd_intf_pins axi_ethernet_0/m_axis_rxs] [get_bd_intf_pins axi_ethernet_0_dma/S_AXIS_STS] + connect_bd_intf_net -intf_net axi_ethernet_0_mdio [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernet_0/mdio] + connect_bd_intf_net -intf_net axi_ethernet_0_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet_0/sgmii] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports dip_switches_8bits] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports lcd_7bits] [get_bd_intf_pins axi_gpio_1/GPIO] + connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports led_8bits] [get_bd_intf_pins axi_gpio_2/GPIO] + connect_bd_intf_net -intf_net axi_gpio_3_GPIO [get_bd_intf_ports push_buttons_5bits] [get_bd_intf_pins axi_gpio_3/GPIO] + connect_bd_intf_net -intf_net axi_gpio_4_GPIO [get_bd_intf_ports rotary_switch] [get_bd_intf_pins axi_gpio_4/GPIO] + connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_0/IIC] + connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_mem_intercon/M00_AXI] + connect_bd_intf_net -intf_net axi_mem_intercon_M01_AXI [get_bd_intf_pins axi_mem_intercon/M01_AXI] [get_bd_intf_pins mig_7series_0/S_AXI] + connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports rs232_uart] [get_bd_intf_pins axi_uart16550_0/UART] + connect_bd_intf_net -intf_net gtxe2_top_0_SI5324_OUT [get_bd_intf_ports SI5324_OUT] [get_bd_intf_pins gtxe2_top_0/SI5324_OUT] + connect_bd_intf_net -intf_net gtxe2_top_0_SMA_OUT [get_bd_intf_ports SMA_OUT] [get_bd_intf_pins gtxe2_top_0/SMA_OUT] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC] + connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M07_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M08_AXI [get_bd_intf_pins axi_gpio_4/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M08_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M09_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M09_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M10_AXI [get_bd_intf_pins axi_usb2_device_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M10_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M11_AXI [get_bd_intf_pins microblaze_0_axi_periph/M11_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M12_AXI [get_bd_intf_pins axi_ethernet_0/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M12_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M13_AXI [get_bd_intf_pins axi_ethernet_0_dma/S_AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M13_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M14_AXI [get_bd_intf_pins axi_emc_0/S_AXI_MEM] [get_bd_intf_pins microblaze_0_axi_periph/M14_AXI] + connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] + connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] + connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] + connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt] + connect_bd_intf_net -intf_net microblaze_0_mdm_axi [get_bd_intf_pins mdm_1/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] + connect_bd_intf_net -intf_net sgmii_mgt_clk_1 [get_bd_intf_ports sgmii_mgt_clk] [get_bd_intf_pins axi_ethernet_0/mgt_clk] + connect_bd_intf_net -intf_net sys_diff_clock_1 [get_bd_intf_ports sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK] + + # Create port connections + connect_bd_net -net axi_ethernet_0_dma_mm2s_cntrl_reset_out_n [get_bd_pins axi_ethernet_0/axi_txc_arstn] [get_bd_pins axi_ethernet_0_dma/mm2s_cntrl_reset_out_n] + connect_bd_net -net axi_ethernet_0_dma_mm2s_introut [get_bd_pins axi_ethernet_0_dma/mm2s_introut] [get_bd_pins microblaze_0_xlconcat/In5] + connect_bd_net -net axi_ethernet_0_dma_mm2s_prmry_reset_out_n [get_bd_pins axi_ethernet_0/axi_txd_arstn] [get_bd_pins axi_ethernet_0_dma/mm2s_prmry_reset_out_n] + connect_bd_net -net axi_ethernet_0_dma_s2mm_introut [get_bd_pins axi_ethernet_0_dma/s2mm_introut] [get_bd_pins microblaze_0_xlconcat/In6] + connect_bd_net -net axi_ethernet_0_dma_s2mm_prmry_reset_out_n [get_bd_pins axi_ethernet_0/axi_rxd_arstn] [get_bd_pins axi_ethernet_0_dma/s2mm_prmry_reset_out_n] + connect_bd_net -net axi_ethernet_0_dma_s2mm_sts_reset_out_n [get_bd_pins axi_ethernet_0/axi_rxs_arstn] [get_bd_pins axi_ethernet_0_dma/s2mm_sts_reset_out_n] + connect_bd_net -net axi_ethernet_0_interrupt [get_bd_pins axi_ethernet_0/interrupt] [get_bd_pins microblaze_0_xlconcat/In4] + connect_bd_net -net axi_ethernet_0_phy_rst_n [get_bd_ports phy_reset_out] [get_bd_pins axi_ethernet_0/phy_rst_n] + connect_bd_net -net axi_ethernet_0_refclk_clk_out1 [get_bd_pins axi_ethernet_0/ref_clk] [get_bd_pins axi_ethernet_0_refclk/clk_out1] + connect_bd_net -net axi_iic_0_gpo [get_bd_ports iic_mux_reset_b] [get_bd_pins axi_iic_0/gpo] + connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In1] + connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins microblaze_0_xlconcat/In3] + connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins microblaze_0_xlconcat/In2] + connect_bd_net -net axi_usb2_device_0_usb_irpt [get_bd_pins axi_usb2_device_0/usb_irpt] [get_bd_pins microblaze_0_xlconcat/In7] + connect_bd_net -net mdm_1_Interrupt [get_bd_pins mdm_1/Interrupt] [get_bd_pins microblaze_0_xlconcat/In0] + connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_mig_7series_0_100M/mb_debug_sys_rst] + connect_bd_net -net microblaze_0_Clk_1 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_emc_0/rdclk] [get_bd_pins axi_emc_0/s_axi_aclk] [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins axi_ethernet_0_dma/m_axi_mm2s_aclk] [get_bd_pins axi_ethernet_0_dma/m_axi_s2mm_aclk] [get_bd_pins axi_ethernet_0_dma/m_axi_sg_aclk] [get_bd_pins axi_ethernet_0_dma/s_axi_lite_aclk] [get_bd_pins axi_ethernet_0_refclk/clk_in1] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_4/s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_mem_intercon/S02_ACLK] [get_bd_pins axi_mem_intercon/S03_ACLK] [get_bd_pins axi_mem_intercon/S04_ACLK] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins axi_usb2_device_0/s_axi_aclk] [get_bd_pins mdm_1/S_AXI_ACLK] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/M08_ACLK] [get_bd_pins microblaze_0_axi_periph/M09_ACLK] [get_bd_pins microblaze_0_axi_periph/M10_ACLK] [get_bd_pins microblaze_0_axi_periph/M11_ACLK] [get_bd_pins microblaze_0_axi_periph/M12_ACLK] [get_bd_pins microblaze_0_axi_periph/M13_ACLK] [get_bd_pins microblaze_0_axi_periph/M14_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins mig_7series_0/ui_addn_clk_0] [get_bd_pins rst_mig_7series_0_100M/slowest_sync_clk] [get_bd_pins xadc_wiz_0/s_axi_aclk] + connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout] + connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_pins mig_7series_0/init_calib_complete] [get_bd_pins rst_mig_7series_0_100M/aux_reset_in] [get_bd_pins rst_mig_7series_0_200M/aux_reset_in] + connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_mig_7series_0_100M/dcm_locked] [get_bd_pins rst_mig_7series_0_200M/dcm_locked] + connect_bd_net -net mig_7series_0_ui_clk [get_bd_pins axi_mem_intercon/M01_ACLK] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_mig_7series_0_200M/slowest_sync_clk] + connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_mig_7series_0_100M/ext_reset_in] [get_bd_pins rst_mig_7series_0_200M/ext_reset_in] + connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins mig_7series_0/sys_rst] + connect_bd_net -net rst_mig_7series_0_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_mig_7series_0_100M/bus_struct_reset] + connect_bd_net -net rst_mig_7series_0_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_mig_7series_0_100M/interconnect_aresetn] + connect_bd_net -net rst_mig_7series_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_mig_7series_0_100M/mb_reset] + connect_bd_net -net rst_mig_7series_0_100M_peripheral_aresetn1 [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_emc_0/s_axi_aresetn] [get_bd_pins axi_ethernet_0/s_axi_lite_resetn] [get_bd_pins axi_ethernet_0_dma/axi_resetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_4/s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_mem_intercon/S02_ARESETN] [get_bd_pins axi_mem_intercon/S03_ARESETN] [get_bd_pins axi_mem_intercon/S04_ARESETN] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins axi_usb2_device_0/s_axi_aresetn] [get_bd_pins mdm_1/S_AXI_ARESETN] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/M08_ARESETN] [get_bd_pins microblaze_0_axi_periph/M09_ARESETN] [get_bd_pins microblaze_0_axi_periph/M10_ARESETN] [get_bd_pins microblaze_0_axi_periph/M11_ARESETN] [get_bd_pins microblaze_0_axi_periph/M12_ARESETN] [get_bd_pins microblaze_0_axi_periph/M13_ARESETN] [get_bd_pins microblaze_0_axi_periph/M14_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_mig_7series_0_100M/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn] + connect_bd_net -net rst_mig_7series_0_200M_peripheral_aresetn [get_bd_pins axi_mem_intercon/M01_ARESETN] [get_bd_pins rst_mig_7series_0_200M/peripheral_aresetn] + connect_bd_net -net xadc_wiz_0_ip2intc_irpt [get_bd_pins microblaze_0_xlconcat/In8] [get_bd_pins xadc_wiz_0/ip2intc_irpt] + connect_bd_net -net xadc_wiz_0_temp_out [get_bd_pins mig_7series_0/device_temp_i] [get_bd_pins xadc_wiz_0/temp_out] + connect_bd_net -net xlconstant_0_const [get_bd_ports DDR3_A14] [get_bd_ports DDR3_A15] [get_bd_ports DDR3_CKE1] [get_bd_ports DDR3_CLK1_P] [get_bd_ports DDR3_ODT1] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_1_const [get_bd_ports DDR3_CLK1_N] [get_bd_ports DDR3_S1_B] [get_bd_ports SM_FAN_PWM] [get_bd_pins xlconstant_1/dout] + + # Create address segments + create_bd_addr_seg -range 0x00100000 -offset 0xC0000000 [get_bd_addr_spaces axi_ethernet_0_dma/Data_SG] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0xC0000000 [get_bd_addr_spaces axi_ethernet_0_dma/Data_MM2S] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0xC0000000 [get_bd_addr_spaces axi_ethernet_0_dma/Data_S2MM] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_0_dma/Data_SG] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr + create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_0_dma/Data_MM2S] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr + create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_0_dma/Data_S2MM] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr + create_bd_addr_seg -range 0x00100000 -offset 0xC0000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0xC0000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x08000000 -offset 0x60000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_emc_0/S_AXI_MEM/MEM0] SEG_axi_emc_0_MEM0 + create_bd_addr_seg -range 0x00040000 -offset 0x40C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] SEG_axi_ethernet_0_Reg0 + create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernet_0_dma/S_AXI_LITE/Reg] SEG_axi_ethernet_0_dma_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_2/S_AXI/Reg] SEG_axi_gpio_2_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40030000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40040000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_4/S_AXI/Reg] SEG_axi_gpio_4_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40800000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] SEG_axi_uart16550_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x44800000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_usb2_device_0/S_AXI/Reg] SEG_axi_usb2_device_0_Reg + create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem + create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem + create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mdm_1/S_AXI/Reg] SEG_mdm_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_axi_intc/S_AXI/Reg] SEG_microblaze_0_axi_intc_Reg + create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr + create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] SEG_xadc_wiz_0_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_system() + + +cr_bd_system "" +set_property EXCLUDE_DEBUG_LOGIC "0" [get_files system.bd ] +set_property GENERATE_SYNTH_CHECKPOINT "0" [get_files system.bd ] +set_property IS_ENABLED "1" [get_files system.bd ] +set_property IS_GLOBAL_INCLUDE "0" [get_files system.bd ] +set_property IS_LOCKED "0" [get_files system.bd ] +set_property LIBRARY "xil_defaultlib" [get_files system.bd ] +set_property PATH_MODE "RelativeFirst" [get_files system.bd ] +set_property PFM_NAME "" [get_files system.bd ] +set_property SYNTH_CHECKPOINT_MODE "None" [get_files system.bd ] +set_property USED_IN "synthesis implementation simulation" [get_files system.bd ] +set_property USED_IN_IMPLEMENTATION "1" [get_files system.bd ] +set_property USED_IN_SIMULATION "1" [get_files system.bd ] +set_property USED_IN_SYNTHESIS "1" [get_files system.bd ] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7vx485tffg1761-2 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2015" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs synth_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "flow" -value "Vivado Synthesis 2015" -objects $obj +set_property -name "name" -value "synth_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj +set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj +set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj +set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj +set_property -name "steps.synth_design.args.fanout_limit" -value "10000" -objects $obj +set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj +set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj +set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj +set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj +set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj +set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj +set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj +set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj +set_property -name "steps.synth_design.args.more options" -value "" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7vx485tffg1761-2 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2015" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.pblocks" -value "" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.slr" -value "0" -objects $obj +set_property -name "options.packthru" -value "0" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.hierarchical_percentages" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.verbose" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.upgrade_cw" -value "0" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.ruledecks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.checks" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.advisory" -value "0" -objects $obj +set_property -name "options.xpe" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.of_objects" -value "" -objects $obj +set_property -name "options.route_type" -value "" -objects $obj +set_property -name "options.list_all_nets" -value "0" -objects $obj +set_property -name "options.show_all" -value "0" -objects $obj +set_property -name "options.has_routing" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "0" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.cells" -value "" -objects $obj +set_property -name "options.hierarchical" -value "0" -objects $obj +set_property -name "options.hierarchical_depth" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.write_xdc" -value "0" -objects $obj +set_property -name "options.clock_roots_only" -value "0" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "1" -objects $obj +set_property -name "options.check_timing_verbose" -value "0" -objects $obj +set_property -name "options.delay_type" -value "" -objects $obj +set_property -name "options.setup" -value "0" -objects $obj +set_property -name "options.hold" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.nworst" -value "" -objects $obj +set_property -name "options.unique_pins" -value "0" -objects $obj +set_property -name "options.path_type" -value "" -objects $obj +set_property -name "options.slack_lesser_than" -value "" -objects $obj +set_property -name "options.report_unconstrained" -value "0" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj +set_property -name "options.significant_digits" -value "" -objects $obj +set_property -name "options.cell" -value "" -objects $obj +set_property -name "options.more_options" -value "" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "constrset" -value "constrs_1" -objects $obj +set_property -name "description" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "flow" -value "Vivado Implementation 2015" -objects $obj +set_property -name "name" -value "impl_1" -objects $obj +set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "pr_configuration" -value "" -objects $obj +set_property -name "srcset" -value "sources_1" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "include_in_archive" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.place_design.tcl.post" -value "" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.place_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.route_design.tcl.post" -value "" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.route_design.args.more options" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj +set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj +set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +#close_project + +puts "INFO: Project created:$project_name" diff --git a/ProjectVC/project_01/sources/constrs/system.xdc b/ProjectVC/project_01/sources/constrs/system.xdc new file mode 100644 index 0000000..7898c08 --- /dev/null +++ b/ProjectVC/project_01/sources/constrs/system.xdc @@ -0,0 +1,100 @@ +set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property CONFIG_MODE BPI16 [current_design] +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design]system.xdc + +set_property PACKAGE_PIN AY32 [get_ports ULPI_clk] +set_property IOSTANDARD LVCMOS18 [get_ports ULPI_clk] + +set_property PACKAGE_PIN BB33 [get_ports ULPI_dir] +set_property IOSTANDARD LVCMOS18 [get_ports ULPI_dir] + +set_property PACKAGE_PIN BA35 [get_ports ULPI_next] +set_property IOSTANDARD LVCMOS18 [get_ports ULPI_next] + +set_property PACKAGE_PIN BB36 [get_ports ULPI_rst] +set_property IOSTANDARD LVCMOS18 [get_ports ULPI_rst] + +set_property PACKAGE_PIN BB32 [get_ports ULPI_stop] +set_property IOSTANDARD LVCMOS18 [get_ports ULPI_stop] + +set_property PACKAGE_PIN AV36 [get_ports {ULPI_data_io[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[0]}] + +set_property PACKAGE_PIN AW36 [get_ports {ULPI_data_io[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[1]}] + +set_property PACKAGE_PIN BA34 [get_ports {ULPI_data_io[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[2]}] + +set_property PACKAGE_PIN BB34 [get_ports {ULPI_data_io[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[3]}] + +set_property PACKAGE_PIN BA36 [get_ports {ULPI_data_io[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[4]}] + +set_property PACKAGE_PIN AT34 [get_ports {ULPI_data_io[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[5]}] + +set_property PACKAGE_PIN AY35 [get_ports {ULPI_data_io[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[6]}] + +set_property PACKAGE_PIN AW35 [get_ports {ULPI_data_io[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {ULPI_data_io[7]}] + +set_property PACKAGE_PIN AY42 [get_ports {iic_mux_reset_b[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {iic_mux_reset_b[0]}] + +set_property PACKAGE_PIN AT36 [get_ports {iic_mux_reset_b[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {iic_mux_reset_b[1]}] + +set_property PACKAGE_PIN AN38 [get_ports Vaux0_v_p] +set_property IOSTANDARD LVCMOS18 [get_ports Vaux0_v_p] + +set_property PACKAGE_PIN AP38 [get_ports Vaux0_v_n] +set_property IOSTANDARD LVCMOS18 [get_ports Vaux0_v_n] + +set_property PACKAGE_PIN AM41 [get_ports Vaux8_v_p] +set_property IOSTANDARD LVCMOS18 [get_ports Vaux8_v_p] + +set_property PACKAGE_PIN AM42 [get_ports Vaux8_v_n] +set_property IOSTANDARD LVCMOS18 [get_ports Vaux8_v_n] + +set_property PACKAGE_PIN BA37 [get_ports SM_FAN_PWM] +set_property IOSTANDARD LVCMOS18 [get_ports SM_FAN_PWM] + +set_property PACKAGE_PIN AD8 [get_ports SI5324_IN_clk_p] + +set_property PACKAGE_PIN AK34 [get_ports USER_CLOCK_IN_clk_p] +set_property IOSTANDARD LVDS [get_ports USER_CLOCK_IN_clk_p] + +set_property PACKAGE_PIN AW32 [get_ports SI5324_OUT_clk_p] +set_property IOSTANDARD LVDS [get_ports SI5324_OUT_clk_p] + +set_property PACKAGE_PIN AN31 [get_ports SMA_OUT_clk_p] +set_property IOSTANDARD LVDS [get_ports SMA_OUT_clk_p] + +set_property PACKAGE_PIN G19 [get_ports DDR3_CLK1_P] +set_property IOSTANDARD SSTL15 [get_ports DDR3_CLK1_P] + +set_property PACKAGE_PIN F19 [get_ports DDR3_CLK1_N] +set_property IOSTANDARD SSTL15 [get_ports DDR3_CLK1_N] + +set_property PACKAGE_PIN J18 [get_ports DDR3_CKE1] +set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1] + +set_property PACKAGE_PIN J20 [get_ports DDR3_S1_B] +set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B] + +set_property PACKAGE_PIN H18 [get_ports DDR3_ODT1] +set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1] + +set_property PACKAGE_PIN F17 [get_ports DDR3_A14] +set_property IOSTANDARD SSTL15 [get_ports DDR3_A14] + +set_property PACKAGE_PIN E17 [get_ports DDR3_A15] +set_property IOSTANDARD SSTL15 [get_ports DDR3_A15] + diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/component.xml b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/component.xml new file mode 100644 index 0000000..641adfd --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/component.xml @@ -0,0 +1,354 @@ + + + xilinx.com + user + gtxe2_top + 1.0 + + + SI5324_OUT + user_clock + + + + + + + CLK_P + + + si5324_out_p + + + + + CLK_N + + + si5324_out_n + + + + + + SMA_OUT + + + + + + + CLK_P + + + SMA_out_p + + + + + CLK_N + + + SMA_out_n + + + + + + USER_CLOCK_IN + + + + + + + CLK_P + + + user_clock_p + + + + + CLK_N + + + user_clock_n + + + + + + SI5324_IN + + + + + + + CLK_P + + + si5324_in_p + + + + + CLK_N + + + si5324_in_n + + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + gtxe2_top + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + 0a690b65 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + gtxe2_top + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 0a690b65 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f64a5dae + + + + + + + user_clock_p + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + user_clock_n + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + si5324_out_p + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + si5324_out_n + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + si5324_in_p + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + si5324_in_n + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + SMA_out_p + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + SMA_out_n + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + src/gtxe2_top.v + verilogSource + IMPORTED_FILE + CHECKSUM_0a690b65 + + + + xilinx_verilogbehavioralsimulation_view_fileset + + src/gtxe2_top.v + verilogSource + IMPORTED_FILE + + + + xilinx_xpgui_view_fileset + + xgui/gtxe2_top_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_f92e9879 + + + + gtxe2_top_v1_0 + + + Component_Name + gtxe2_top_v1_0 + + + + + + artix7 + kintex7 + virtex7 + + + /UserIP + + gtxe2_top_v1_0 + 4 + 2015-04-07T08:40:29Z + + C:/file_repository_2015.1/common/gtxe2_top_v1_00_a + + + + 2015.1 + + + + + + + diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/src/gtxe2_top.v b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/src/gtxe2_top.v new file mode 100644 index 0000000..0a441f3 --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/src/gtxe2_top.v @@ -0,0 +1,110 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:58:09 02/02/2012 +// Design Name: +// Module Name: gtxe2_top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module gtxe2_top( + input user_clock_p, + input user_clock_n, + output si5324_out_p, + output si5324_out_n, + input si5324_in_p, + input si5324_in_n, + output SMA_out_p, + output SMA_out_n + ); + + + wire clk_out; +wire clock_bufg; + +reg q; + +IBUFDS IBUFDS_inst_user_clock( + .O(clock_out), // Buffer output + .I(user_clock_p), // Diff_p buffer input (connect directly to top-level port) + .IB(user_clock_n) // Diff_n buffer input (connect directly to top-level port) +); + +BUFG BUFG_inst_user_clock ( + .O(clock_bufg), // 1-bit output: Clock output + .I(clock_out) + ); + + + ODDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) ODDR_out_clock_inst_user_clock ( + .Q(clock_out_ddr), // 1-bit DDR output + .C(clock_bufg), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D1(1'b1), // 1-bit data input (positive edge) + .D2(1'b0), // 1-bit data input (negative edge) + .R(), // 1-bit reset + .S() // 1-bit set + ); + + +OBUFDS OBUFDS_inst_user_clock ( + .O (si5324_out_p), // Diff_p output (connect directly to top-level port) + .OB(si5324_out_n), // Diff_n output (connect directly to top-level port) + .I (clock_out_ddr) // Buffer input + ); + + +IBUFDS_GTE2 IBUFDS_GTE2_inst_si5324( + .O (clock_out_si5324), // Buffer output + .I (si5324_in_p), // Diff_p buffer input (connect directly to top-level port) + .IB(si5324_in_n) // Diff_n buffer input (connect directly to top-level port) +); + + +BUFG BUFG_inst_si5324 ( + .O(clock_bufg_si5324), // 1-bit output: Clock output + .I(clock_out_si5324) + ); + + + ODDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) ODDR_out_clock_si5324 ( + .Q(clock_out_ddr_si5324), // 1-bit DDR output + .C(clock_bufg_si5324), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D1(1'b1), // 1-bit data input (positive edge) + .D2(1'b0), // 1-bit data input (negative edge) + .R(), // 1-bit reset + .S() // 1-bit set + ); + +OBUFDS #( + .IOSTANDARD("DEFAULT"), // Specify the output I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) OBUFDS_inst_si5324 ( + .O (SMA_out_p), // Diff_p output (connect directly to top-level port) + .OB(SMA_out_n), // Diff_n output (connect directly to top-level port) + .I (clock_out_ddr_si5324) // Buffer input + ); + + + +endmodule diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/java_command_handlers.wdf b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/java_command_handlers.wdf new file mode 100644 index 0000000..e1bc7e9 --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/java_command_handlers.wdf @@ -0,0 +1,3 @@ +version:1 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:2d31:00:00 +eof:3471413770 diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/webtalk_pa.xml b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..035b955 --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.cache/wt/webtalk_pa.xml @@ -0,0 +1,29 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + +
+ + diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.hw/tmp_edit_project.lpr b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.hw/tmp_edit_project.lpr new file mode 100644 index 0000000..c25d3b9 --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.hw/tmp_edit_project.lpr @@ -0,0 +1,2 @@ + + diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.xpr b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.xpr new file mode 100644 index 0000000..b0b5e84 --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/tmp_edit_project.xpr @@ -0,0 +1,102 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + Vivado Implementation Defaults + + + + + + + + + + + + + + diff --git a/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/xgui/gtxe2_top_v1_0.tcl b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/xgui/gtxe2_top_v1_0.tcl new file mode 100644 index 0000000..0db18e9 --- /dev/null +++ b/ProjectVC/project_01/sources/gtxe2_top_v1_00_a/xgui/gtxe2_top_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/ProjectVC/project_01/sources/hdl/system_wrapper.v b/ProjectVC/project_01/sources/hdl/system_wrapper.v new file mode 100644 index 0000000..92ea409 --- /dev/null +++ b/ProjectVC/project_01/sources/hdl/system_wrapper.v @@ -0,0 +1,541 @@ +//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +//Date : Fri Jan 26 19:13:14 2018 +//Host : LAPTOP-AKMF2NBQ running 64-bit major release (build 9200) +//Command : generate_target system_wrapper.bd +//Design : system_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module system_wrapper + (DDR3_A14, + DDR3_A15, + DDR3_CKE1, + DDR3_CLK1_N, + DDR3_CLK1_P, + DDR3_ODT1, + DDR3_S1_B, + SI5324_IN_clk_n, + SI5324_IN_clk_p, + SI5324_OUT_clk_n, + SI5324_OUT_clk_p, + SMA_OUT_clk_n, + SMA_OUT_clk_p, + SM_FAN_PWM, + ULPI_clk, + ULPI_data_io, + ULPI_dir, + ULPI_next, + ULPI_rst, + ULPI_stop, + USER_CLOCK_IN_clk_n, + USER_CLOCK_IN_clk_p, + Vaux0_v_n, + Vaux0_v_p, + Vaux8_v_n, + Vaux8_v_p, + Vp_Vn_v_n, + Vp_Vn_v_p, + ddr3_sdram_addr, + ddr3_sdram_ba, + ddr3_sdram_cas_n, + ddr3_sdram_ck_n, + ddr3_sdram_ck_p, + ddr3_sdram_cke, + ddr3_sdram_cs_n, + ddr3_sdram_dm, + ddr3_sdram_dq, + ddr3_sdram_dqs_n, + ddr3_sdram_dqs_p, + ddr3_sdram_odt, + ddr3_sdram_ras_n, + ddr3_sdram_reset_n, + ddr3_sdram_we_n, + dip_switches_8bits_tri_i, + iic_main_scl_io, + iic_main_sda_io, + iic_mux_reset_b, + lcd_7bits_tri_o, + led_8bits_tri_o, + linear_flash_addr, + linear_flash_adv_ldn, + linear_flash_ce_n, + linear_flash_dq_io, + linear_flash_oen, + linear_flash_wen, + mdio_mdc_mdc, + mdio_mdc_mdio_io, + phy_reset_out, + push_buttons_5bits_tri_i, + reset, + rotary_switch_tri_i, + rs232_uart_rxd, + rs232_uart_txd, + sgmii_mgt_clk_clk_n, + sgmii_mgt_clk_clk_p, + sgmii_rxn, + sgmii_rxp, + sgmii_txn, + sgmii_txp, + sys_diff_clock_clk_n, + sys_diff_clock_clk_p); + output [0:0]DDR3_A14; + output [0:0]DDR3_A15; + output [0:0]DDR3_CKE1; + output [0:0]DDR3_CLK1_N; + output [0:0]DDR3_CLK1_P; + output [0:0]DDR3_ODT1; + output [0:0]DDR3_S1_B; + input SI5324_IN_clk_n; + input SI5324_IN_clk_p; + output SI5324_OUT_clk_n; + output SI5324_OUT_clk_p; + output SMA_OUT_clk_n; + output SMA_OUT_clk_p; + output [0:0]SM_FAN_PWM; + input ULPI_clk; + inout [7:0]ULPI_data_io; + input ULPI_dir; + input ULPI_next; + output ULPI_rst; + output ULPI_stop; + input USER_CLOCK_IN_clk_n; + input USER_CLOCK_IN_clk_p; + input Vaux0_v_n; + input Vaux0_v_p; + input Vaux8_v_n; + input Vaux8_v_p; + input Vp_Vn_v_n; + input Vp_Vn_v_p; + output [13:0]ddr3_sdram_addr; + output [2:0]ddr3_sdram_ba; + output ddr3_sdram_cas_n; + output [0:0]ddr3_sdram_ck_n; + output [0:0]ddr3_sdram_ck_p; + output [0:0]ddr3_sdram_cke; + output [0:0]ddr3_sdram_cs_n; + output [7:0]ddr3_sdram_dm; + inout [63:0]ddr3_sdram_dq; + inout [7:0]ddr3_sdram_dqs_n; + inout [7:0]ddr3_sdram_dqs_p; + output [0:0]ddr3_sdram_odt; + output ddr3_sdram_ras_n; + output ddr3_sdram_reset_n; + output ddr3_sdram_we_n; + input [7:0]dip_switches_8bits_tri_i; + inout iic_main_scl_io; + inout iic_main_sda_io; + output [1:0]iic_mux_reset_b; + output [6:0]lcd_7bits_tri_o; + output [7:0]led_8bits_tri_o; + output [26:1]linear_flash_addr; + output linear_flash_adv_ldn; + output linear_flash_ce_n; + inout [15:0]linear_flash_dq_io; + output linear_flash_oen; + output linear_flash_wen; + output mdio_mdc_mdc; + inout mdio_mdc_mdio_io; + output [0:0]phy_reset_out; + input [4:0]push_buttons_5bits_tri_i; + input reset; + input [2:0]rotary_switch_tri_i; + input rs232_uart_rxd; + output rs232_uart_txd; + input sgmii_mgt_clk_clk_n; + input sgmii_mgt_clk_clk_p; + input sgmii_rxn; + input sgmii_rxp; + output sgmii_txn; + output sgmii_txp; + input sys_diff_clock_clk_n; + input sys_diff_clock_clk_p; + + wire [0:0]DDR3_A14; + wire [0:0]DDR3_A15; + wire [0:0]DDR3_CKE1; + wire [0:0]DDR3_CLK1_N; + wire [0:0]DDR3_CLK1_P; + wire [0:0]DDR3_ODT1; + wire [0:0]DDR3_S1_B; + wire SI5324_IN_clk_n; + wire SI5324_IN_clk_p; + wire SI5324_OUT_clk_n; + wire SI5324_OUT_clk_p; + wire SMA_OUT_clk_n; + wire SMA_OUT_clk_p; + wire [0:0]SM_FAN_PWM; + wire ULPI_clk; + wire [0:0]ULPI_data_i_0; + wire [1:1]ULPI_data_i_1; + wire [2:2]ULPI_data_i_2; + wire [3:3]ULPI_data_i_3; + wire [4:4]ULPI_data_i_4; + wire [5:5]ULPI_data_i_5; + wire [6:6]ULPI_data_i_6; + wire [7:7]ULPI_data_i_7; + wire [0:0]ULPI_data_io_0; + wire [1:1]ULPI_data_io_1; + wire [2:2]ULPI_data_io_2; + wire [3:3]ULPI_data_io_3; + wire [4:4]ULPI_data_io_4; + wire [5:5]ULPI_data_io_5; + wire [6:6]ULPI_data_io_6; + wire [7:7]ULPI_data_io_7; + wire [0:0]ULPI_data_o_0; + wire [1:1]ULPI_data_o_1; + wire [2:2]ULPI_data_o_2; + wire [3:3]ULPI_data_o_3; + wire [4:4]ULPI_data_o_4; + wire [5:5]ULPI_data_o_5; + wire [6:6]ULPI_data_o_6; + wire [7:7]ULPI_data_o_7; + wire ULPI_data_t; + wire ULPI_dir; + wire ULPI_next; + wire ULPI_rst; + wire ULPI_stop; + wire USER_CLOCK_IN_clk_n; + wire USER_CLOCK_IN_clk_p; + wire Vaux0_v_n; + wire Vaux0_v_p; + wire Vaux8_v_n; + wire Vaux8_v_p; + wire Vp_Vn_v_n; + wire Vp_Vn_v_p; + wire [13:0]ddr3_sdram_addr; + wire [2:0]ddr3_sdram_ba; + wire ddr3_sdram_cas_n; + wire [0:0]ddr3_sdram_ck_n; + wire [0:0]ddr3_sdram_ck_p; + wire [0:0]ddr3_sdram_cke; + wire [0:0]ddr3_sdram_cs_n; + wire [7:0]ddr3_sdram_dm; + wire [63:0]ddr3_sdram_dq; + wire [7:0]ddr3_sdram_dqs_n; + wire [7:0]ddr3_sdram_dqs_p; + wire [0:0]ddr3_sdram_odt; + wire ddr3_sdram_ras_n; + wire ddr3_sdram_reset_n; + wire ddr3_sdram_we_n; + wire [7:0]dip_switches_8bits_tri_i; + wire iic_main_scl_i; + wire iic_main_scl_io; + wire iic_main_scl_o; + wire iic_main_scl_t; + wire iic_main_sda_i; + wire iic_main_sda_io; + wire iic_main_sda_o; + wire iic_main_sda_t; + wire [1:0]iic_mux_reset_b; + wire [6:0]lcd_7bits_tri_o; + wire [7:0]led_8bits_tri_o; + wire [26:1]linear_flash_addr; + wire linear_flash_adv_ldn; + wire linear_flash_ce_n; + wire [0:0]linear_flash_dq_i_0; + wire [1:1]linear_flash_dq_i_1; + wire [10:10]linear_flash_dq_i_10; + wire [11:11]linear_flash_dq_i_11; + wire [12:12]linear_flash_dq_i_12; + wire [13:13]linear_flash_dq_i_13; + wire [14:14]linear_flash_dq_i_14; + wire [15:15]linear_flash_dq_i_15; + wire [2:2]linear_flash_dq_i_2; + wire [3:3]linear_flash_dq_i_3; + wire [4:4]linear_flash_dq_i_4; + wire [5:5]linear_flash_dq_i_5; + wire [6:6]linear_flash_dq_i_6; + wire [7:7]linear_flash_dq_i_7; + wire [8:8]linear_flash_dq_i_8; + wire [9:9]linear_flash_dq_i_9; + wire [0:0]linear_flash_dq_io_0; + wire [1:1]linear_flash_dq_io_1; + wire [10:10]linear_flash_dq_io_10; + wire [11:11]linear_flash_dq_io_11; + wire [12:12]linear_flash_dq_io_12; + wire [13:13]linear_flash_dq_io_13; + wire [14:14]linear_flash_dq_io_14; + wire [15:15]linear_flash_dq_io_15; + wire [2:2]linear_flash_dq_io_2; + wire [3:3]linear_flash_dq_io_3; + wire [4:4]linear_flash_dq_io_4; + wire [5:5]linear_flash_dq_io_5; + wire [6:6]linear_flash_dq_io_6; + wire [7:7]linear_flash_dq_io_7; + wire [8:8]linear_flash_dq_io_8; + wire [9:9]linear_flash_dq_io_9; + wire [0:0]linear_flash_dq_o_0; + wire [1:1]linear_flash_dq_o_1; + wire [10:10]linear_flash_dq_o_10; + wire [11:11]linear_flash_dq_o_11; + wire [12:12]linear_flash_dq_o_12; + wire [13:13]linear_flash_dq_o_13; + wire [14:14]linear_flash_dq_o_14; + wire [15:15]linear_flash_dq_o_15; + wire [2:2]linear_flash_dq_o_2; + wire [3:3]linear_flash_dq_o_3; + wire [4:4]linear_flash_dq_o_4; + wire [5:5]linear_flash_dq_o_5; + wire [6:6]linear_flash_dq_o_6; + wire [7:7]linear_flash_dq_o_7; + wire [8:8]linear_flash_dq_o_8; + wire [9:9]linear_flash_dq_o_9; + wire [0:0]linear_flash_dq_t_0; + wire [1:1]linear_flash_dq_t_1; + wire [10:10]linear_flash_dq_t_10; + wire [11:11]linear_flash_dq_t_11; + wire [12:12]linear_flash_dq_t_12; + wire [13:13]linear_flash_dq_t_13; + wire [14:14]linear_flash_dq_t_14; + wire [15:15]linear_flash_dq_t_15; + wire [2:2]linear_flash_dq_t_2; + wire [3:3]linear_flash_dq_t_3; + wire [4:4]linear_flash_dq_t_4; + wire [5:5]linear_flash_dq_t_5; + wire [6:6]linear_flash_dq_t_6; + wire [7:7]linear_flash_dq_t_7; + wire [8:8]linear_flash_dq_t_8; + wire [9:9]linear_flash_dq_t_9; + wire linear_flash_oen; + wire linear_flash_wen; + wire mdio_mdc_mdc; + wire mdio_mdc_mdio_i; + wire mdio_mdc_mdio_io; + wire mdio_mdc_mdio_o; + wire mdio_mdc_mdio_t; + wire [0:0]phy_reset_out; + wire [4:0]push_buttons_5bits_tri_i; + wire reset; + wire [2:0]rotary_switch_tri_i; + wire rs232_uart_rxd; + wire rs232_uart_txd; + wire sgmii_mgt_clk_clk_n; + wire sgmii_mgt_clk_clk_p; + wire sgmii_rxn; + wire sgmii_rxp; + wire sgmii_txn; + wire sgmii_txp; + wire sys_diff_clock_clk_n; + wire sys_diff_clock_clk_p; + + IOBUF ULPI_data_iobuf_0 + (.I(ULPI_data_o_0), + .IO(ULPI_data_io[0]), + .O(ULPI_data_i_0), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_1 + (.I(ULPI_data_o_1), + .IO(ULPI_data_io[1]), + .O(ULPI_data_i_1), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_2 + (.I(ULPI_data_o_2), + .IO(ULPI_data_io[2]), + .O(ULPI_data_i_2), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_3 + (.I(ULPI_data_o_3), + .IO(ULPI_data_io[3]), + .O(ULPI_data_i_3), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_4 + (.I(ULPI_data_o_4), + .IO(ULPI_data_io[4]), + .O(ULPI_data_i_4), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_5 + (.I(ULPI_data_o_5), + .IO(ULPI_data_io[5]), + .O(ULPI_data_i_5), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_6 + (.I(ULPI_data_o_6), + .IO(ULPI_data_io[6]), + .O(ULPI_data_i_6), + .T(ULPI_data_t)); + IOBUF ULPI_data_iobuf_7 + (.I(ULPI_data_o_7), + .IO(ULPI_data_io[7]), + .O(ULPI_data_i_7), + .T(ULPI_data_t)); + IOBUF iic_main_scl_iobuf + (.I(iic_main_scl_o), + .IO(iic_main_scl_io), + .O(iic_main_scl_i), + .T(iic_main_scl_t)); + IOBUF iic_main_sda_iobuf + (.I(iic_main_sda_o), + .IO(iic_main_sda_io), + .O(iic_main_sda_i), + .T(iic_main_sda_t)); + IOBUF linear_flash_dq_iobuf_0 + (.I(linear_flash_dq_o_0), + .IO(linear_flash_dq_io[0]), + .O(linear_flash_dq_i_0), + .T(linear_flash_dq_t_0)); + IOBUF linear_flash_dq_iobuf_1 + (.I(linear_flash_dq_o_1), + .IO(linear_flash_dq_io[1]), + .O(linear_flash_dq_i_1), + .T(linear_flash_dq_t_1)); + IOBUF linear_flash_dq_iobuf_10 + (.I(linear_flash_dq_o_10), + .IO(linear_flash_dq_io[10]), + .O(linear_flash_dq_i_10), + .T(linear_flash_dq_t_10)); + IOBUF linear_flash_dq_iobuf_11 + (.I(linear_flash_dq_o_11), + .IO(linear_flash_dq_io[11]), + .O(linear_flash_dq_i_11), + .T(linear_flash_dq_t_11)); + IOBUF linear_flash_dq_iobuf_12 + (.I(linear_flash_dq_o_12), + .IO(linear_flash_dq_io[12]), + .O(linear_flash_dq_i_12), + .T(linear_flash_dq_t_12)); + IOBUF linear_flash_dq_iobuf_13 + (.I(linear_flash_dq_o_13), + .IO(linear_flash_dq_io[13]), + .O(linear_flash_dq_i_13), + .T(linear_flash_dq_t_13)); + IOBUF linear_flash_dq_iobuf_14 + (.I(linear_flash_dq_o_14), + .IO(linear_flash_dq_io[14]), + .O(linear_flash_dq_i_14), + .T(linear_flash_dq_t_14)); + IOBUF linear_flash_dq_iobuf_15 + (.I(linear_flash_dq_o_15), + .IO(linear_flash_dq_io[15]), + .O(linear_flash_dq_i_15), + .T(linear_flash_dq_t_15)); + IOBUF linear_flash_dq_iobuf_2 + (.I(linear_flash_dq_o_2), + .IO(linear_flash_dq_io[2]), + .O(linear_flash_dq_i_2), + .T(linear_flash_dq_t_2)); + IOBUF linear_flash_dq_iobuf_3 + (.I(linear_flash_dq_o_3), + .IO(linear_flash_dq_io[3]), + .O(linear_flash_dq_i_3), + .T(linear_flash_dq_t_3)); + IOBUF linear_flash_dq_iobuf_4 + (.I(linear_flash_dq_o_4), + .IO(linear_flash_dq_io[4]), + .O(linear_flash_dq_i_4), + .T(linear_flash_dq_t_4)); + IOBUF linear_flash_dq_iobuf_5 + (.I(linear_flash_dq_o_5), + .IO(linear_flash_dq_io[5]), + .O(linear_flash_dq_i_5), + .T(linear_flash_dq_t_5)); + IOBUF linear_flash_dq_iobuf_6 + (.I(linear_flash_dq_o_6), + .IO(linear_flash_dq_io[6]), + .O(linear_flash_dq_i_6), + .T(linear_flash_dq_t_6)); + IOBUF linear_flash_dq_iobuf_7 + (.I(linear_flash_dq_o_7), + .IO(linear_flash_dq_io[7]), + .O(linear_flash_dq_i_7), + .T(linear_flash_dq_t_7)); + IOBUF linear_flash_dq_iobuf_8 + (.I(linear_flash_dq_o_8), + .IO(linear_flash_dq_io[8]), + .O(linear_flash_dq_i_8), + .T(linear_flash_dq_t_8)); + IOBUF linear_flash_dq_iobuf_9 + (.I(linear_flash_dq_o_9), + .IO(linear_flash_dq_io[9]), + .O(linear_flash_dq_i_9), + .T(linear_flash_dq_t_9)); + IOBUF mdio_mdc_mdio_iobuf + (.I(mdio_mdc_mdio_o), + .IO(mdio_mdc_mdio_io), + .O(mdio_mdc_mdio_i), + .T(mdio_mdc_mdio_t)); + system system_i + (.DDR3_A14(DDR3_A14), + .DDR3_A15(DDR3_A15), + .DDR3_CKE1(DDR3_CKE1), + .DDR3_CLK1_N(DDR3_CLK1_N), + .DDR3_CLK1_P(DDR3_CLK1_P), + .DDR3_ODT1(DDR3_ODT1), + .DDR3_S1_B(DDR3_S1_B), + .SI5324_IN_clk_n(SI5324_IN_clk_n), + .SI5324_IN_clk_p(SI5324_IN_clk_p), + .SI5324_OUT_clk_n(SI5324_OUT_clk_n), + .SI5324_OUT_clk_p(SI5324_OUT_clk_p), + .SMA_OUT_clk_n(SMA_OUT_clk_n), + .SMA_OUT_clk_p(SMA_OUT_clk_p), + .SM_FAN_PWM(SM_FAN_PWM), + .ULPI_clk(ULPI_clk), + .ULPI_data_i({ULPI_data_i_7,ULPI_data_i_6,ULPI_data_i_5,ULPI_data_i_4,ULPI_data_i_3,ULPI_data_i_2,ULPI_data_i_1,ULPI_data_i_0}), + .ULPI_data_o({ULPI_data_o_7,ULPI_data_o_6,ULPI_data_o_5,ULPI_data_o_4,ULPI_data_o_3,ULPI_data_o_2,ULPI_data_o_1,ULPI_data_o_0}), + .ULPI_data_t(ULPI_data_t), + .ULPI_dir(ULPI_dir), + .ULPI_next(ULPI_next), + .ULPI_rst(ULPI_rst), + .ULPI_stop(ULPI_stop), + .USER_CLOCK_IN_clk_n(USER_CLOCK_IN_clk_n), + .USER_CLOCK_IN_clk_p(USER_CLOCK_IN_clk_p), + .Vaux0_v_n(Vaux0_v_n), + .Vaux0_v_p(Vaux0_v_p), + .Vaux8_v_n(Vaux8_v_n), + .Vaux8_v_p(Vaux8_v_p), + .Vp_Vn_v_n(Vp_Vn_v_n), + .Vp_Vn_v_p(Vp_Vn_v_p), + .ddr3_sdram_addr(ddr3_sdram_addr), + .ddr3_sdram_ba(ddr3_sdram_ba), + .ddr3_sdram_cas_n(ddr3_sdram_cas_n), + .ddr3_sdram_ck_n(ddr3_sdram_ck_n), + .ddr3_sdram_ck_p(ddr3_sdram_ck_p), + .ddr3_sdram_cke(ddr3_sdram_cke), + .ddr3_sdram_cs_n(ddr3_sdram_cs_n), + .ddr3_sdram_dm(ddr3_sdram_dm), + .ddr3_sdram_dq(ddr3_sdram_dq), + .ddr3_sdram_dqs_n(ddr3_sdram_dqs_n), + .ddr3_sdram_dqs_p(ddr3_sdram_dqs_p), + .ddr3_sdram_odt(ddr3_sdram_odt), + .ddr3_sdram_ras_n(ddr3_sdram_ras_n), + .ddr3_sdram_reset_n(ddr3_sdram_reset_n), + .ddr3_sdram_we_n(ddr3_sdram_we_n), + .dip_switches_8bits_tri_i(dip_switches_8bits_tri_i), + .iic_main_scl_i(iic_main_scl_i), + .iic_main_scl_o(iic_main_scl_o), + .iic_main_scl_t(iic_main_scl_t), + .iic_main_sda_i(iic_main_sda_i), + .iic_main_sda_o(iic_main_sda_o), + .iic_main_sda_t(iic_main_sda_t), + .iic_mux_reset_b(iic_mux_reset_b), + .lcd_7bits_tri_o(lcd_7bits_tri_o), + .led_8bits_tri_o(led_8bits_tri_o), + .linear_flash_addr(linear_flash_addr), + .linear_flash_adv_ldn(linear_flash_adv_ldn), + .linear_flash_ce_n(linear_flash_ce_n), + .linear_flash_dq_i({linear_flash_dq_i_15,linear_flash_dq_i_14,linear_flash_dq_i_13,linear_flash_dq_i_12,linear_flash_dq_i_11,linear_flash_dq_i_10,linear_flash_dq_i_9,linear_flash_dq_i_8,linear_flash_dq_i_7,linear_flash_dq_i_6,linear_flash_dq_i_5,linear_flash_dq_i_4,linear_flash_dq_i_3,linear_flash_dq_i_2,linear_flash_dq_i_1,linear_flash_dq_i_0}), + .linear_flash_dq_o({linear_flash_dq_o_15,linear_flash_dq_o_14,linear_flash_dq_o_13,linear_flash_dq_o_12,linear_flash_dq_o_11,linear_flash_dq_o_10,linear_flash_dq_o_9,linear_flash_dq_o_8,linear_flash_dq_o_7,linear_flash_dq_o_6,linear_flash_dq_o_5,linear_flash_dq_o_4,linear_flash_dq_o_3,linear_flash_dq_o_2,linear_flash_dq_o_1,linear_flash_dq_o_0}), + .linear_flash_dq_t({linear_flash_dq_t_15,linear_flash_dq_t_14,linear_flash_dq_t_13,linear_flash_dq_t_12,linear_flash_dq_t_11,linear_flash_dq_t_10,linear_flash_dq_t_9,linear_flash_dq_t_8,linear_flash_dq_t_7,linear_flash_dq_t_6,linear_flash_dq_t_5,linear_flash_dq_t_4,linear_flash_dq_t_3,linear_flash_dq_t_2,linear_flash_dq_t_1,linear_flash_dq_t_0}), + .linear_flash_oen(linear_flash_oen), + .linear_flash_wen(linear_flash_wen), + .mdio_mdc_mdc(mdio_mdc_mdc), + .mdio_mdc_mdio_i(mdio_mdc_mdio_i), + .mdio_mdc_mdio_o(mdio_mdc_mdio_o), + .mdio_mdc_mdio_t(mdio_mdc_mdio_t), + .phy_reset_out(phy_reset_out), + .push_buttons_5bits_tri_i(push_buttons_5bits_tri_i), + .reset(reset), + .rotary_switch_tri_i(rotary_switch_tri_i), + .rs232_uart_rxd(rs232_uart_rxd), + .rs232_uart_txd(rs232_uart_txd), + .sgmii_mgt_clk_clk_n(sgmii_mgt_clk_clk_n), + .sgmii_mgt_clk_clk_p(sgmii_mgt_clk_clk_p), + .sgmii_rxn(sgmii_rxn), + .sgmii_rxp(sgmii_rxp), + .sgmii_txn(sgmii_txn), + .sgmii_txp(sgmii_txp), + .sys_diff_clock_clk_n(sys_diff_clock_clk_n), + .sys_diff_clock_clk_p(sys_diff_clock_clk_p)); +endmodule diff --git a/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/board.prj b/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/board.prj new file mode 100644 index 0000000..e3091f4 --- /dev/null +++ b/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/board.prj @@ -0,0 +1,203 @@ + + + + design_1_mig_7series_1_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7vx485t-ffg1761/-2 + 1.9 + Differential + Use System Clock + ACTIVE HIGH + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6 + 2500 + 1.8V + 4:1 + 200 + 0 + 1 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 512 + 1 + 0 + + + diff --git a/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_a.prj b/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_a.prj new file mode 100644 index 0000000..f30ad62 --- /dev/null +++ b/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_a.prj @@ -0,0 +1,203 @@ + + + + system_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Disabled + xc7vx485t-ffg1761/-2 + 2.3 + Differential + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6 + 1250 + 2.0V + 4:1 + 200 + 1 + 800 + 8.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.5V + 1073741824 + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 30 + 512 + 1 + 0 + + + + diff --git a/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_b.prj b/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_b.prj new file mode 100644 index 0000000..a6615ea --- /dev/null +++ b/ProjectVC/project_01/sources/ip/system_mig_7series_0_0/mig_b.prj @@ -0,0 +1,203 @@ + + + + system_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Disabled + xc7vx485t-ffg1761/-2 + 2.3 + Differential + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6 + 1250 + 2.0V + 4:1 + 200 + 1 + 800 + 8.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.5V + 1073741824 + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 30 + 512 + 3 + 0 + + + +