f4612e06c6
Freeze the IWDG watchdog when cores are halted to prevent a reset while debugging. The PMIC present on some board senses the nsrst and forces a power cycle to the target. The power cycle causes the SWJ-DP to restart in JTAG mode. If the debugger is using SWD, the mismatch triggers an error after the reset command. Ignore the error detected by 'dap init' and proceed executing the handler. The error in 'dap init' will force a reconnect during the following 'dap apid', restoring the SWD functionality. Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6599 Tested-by: jenkins |
||
|---|---|---|
| .. | ||
| board | ||
| chip | ||
| cpld | ||
| cpu | ||
| fpga | ||
| interface | ||
| target | ||
| test | ||
| tools | ||
| bitsbytes.tcl | ||
| mem_helper.tcl | ||
| memory.tcl | ||
| mmr_helpers.tcl | ||