riscv-openocd/tcl
Marek Vasut a38a0afd17 tcl/target: Select default boot core on Renesas R-Car Gen2/Gen3
On SMP Renesas R-Car Gen2/Gen3 systems, select the boot core as
the default target using the 'targets' command. This way, the
user can start debugging code running on the boot core without
having to switch to the boot core by explicitly invoking 'targets'
command first, since it is likely the debugged code will run on
the boot core. Note that most of the code is already in place, it
was just not used, so this is more of a fix to make the original
intention work.

Change-Id: I727808adce617c1d9ebd6ffa34f60f5882cdae60
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26 14:39:22 +01:00
..
board tcl: Add support for the Digilent Nexys Video board 2021-06-23 23:50:58 +01:00
chip tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:49:08 +01:00
cpld xilinx-xc7: Add additional IDCODEs. 2018-10-27 14:37:43 +01:00
cpu tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:48:44 +01:00
fpga tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:49:08 +01:00
interface tcl: remove remaining deprecated commands 2021-05-29 21:34:27 +01:00
target tcl/target: Select default boot core on Renesas R-Car Gen2/Gen3 2021-06-26 14:39:22 +01:00
test tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:48:44 +01:00
tools tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:49:08 +01:00
bitsbytes.tcl tcl: fix some minor typo 2021-05-22 10:06:26 +01:00
mem_helper.tcl tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:48:44 +01:00
memory.tcl tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:49:08 +01:00
mmr_helpers.tcl tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change 2021-05-08 09:49:08 +01:00