6c1e1a212a
according the RM0453, the second core have a different Flash CR and SR registers for flash operations (called C2CR and C2SR). so we need to a different flash_regs than older L4 devices. @see stm32wl_cpu2_flash_regs the C2CR register don't contain LOCK and OPTLOCK bits, and this explain the addition of new register index called STM32_FLASH_CR_WLK_INDEX to look-up the CR with lock, to be used in locking/unlocking the flash. note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1, to solve this read the UID64 (IEEE 64-bit unique device ID register) Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6050 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> |
||
|---|---|---|
| .. | ||
| board | ||
| chip | ||
| cpld | ||
| cpu | ||
| fpga | ||
| interface | ||
| target | ||
| test | ||
| tools | ||
| bitsbytes.tcl | ||
| mem_helper.tcl | ||
| memory.tcl | ||
| mmr_helpers.tcl | ||