82 lines
2.5 KiB
INI
82 lines
2.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Source the ESP common configuration file.
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source [find target/esp_common.cfg]
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# Target specific global variables
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set _CHIPNAME "riscv"
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set _CPUTAPID 0x00005c25
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set _ESP_ARCH "riscv"
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set _ONLYCPU 1
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set _ESP_SMP_TARGET 0
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set _ESP_SMP_BREAK 0
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set _ESP_EFUSE_MAC_ADDR_REG 0x60008844
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# Target specific functions should be implemented for each riscv chips.
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proc riscv_wdt_disable { } {
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# Halt event can occur during config phase (before "init" is done).
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# Ignore it since mww commands don't work at that time.
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if { [string compare [command mode] config] == 0 } {
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return
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}
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# Timer Group 0 & 1 WDTs
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mww 0x6001f064 0x50D83AA1
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mww 0x6001F048 0
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mww 0x60020064 0x50D83AA1
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mww 0x60020048 0
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# RTC WDT
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mww 0x600080a8 0x50D83AA1
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mww 0x60008090 0
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# SWD
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mww 0x600080b0 0x8F1D312A
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mww 0x600080ac 0x84B00000
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}
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# This is almost identical with the esp32c2_soc_reset.
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# Will be refactored with the other common settings.
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proc riscv_soc_reset { } {
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global _RISCV_DMCONTROL
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# This procedure does "digital system reset", i.e. resets
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# all the peripherals except for the RTC block.
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# It is called from reset-assert-post target event callback,
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# after assert_reset procedure was called.
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# Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
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# temporarily take it out of reset. Save the dmcontrol state before
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# doing so.
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riscv dmi_write $_RISCV_DMCONTROL 0x80000001
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# Trigger the reset
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mww 0x60008000 0x9c00a000
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# Workaround for stuck in cpu start during calibration.
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# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
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mww 0x6001F068 0
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# Wait for the reset to happen
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sleep 10
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poll
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# Disable the watchdogs again
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riscv_wdt_disable
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# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
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# We will clean allhalted state by resuming the core.
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riscv dmi_write $_RISCV_DMCONTROL 0x40000001
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# Put the hart back into reset state. Note that we need to keep haltreq set.
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riscv dmi_write $_RISCV_DMCONTROL 0x80000003
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}
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proc riscv_memprot_is_enabled { } {
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# IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10A8 0] != 0 } {
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return 1
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}
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# DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10C0 0] != 0 } {
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return 1
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}
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return 0
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}
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create_esp_target $_ESP_ARCH
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