riscv-openocd/tcl/target/esp32c3.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#

# Source the ESP common configuration file.
source [find target/esp_common.cfg]

# Target specific global variables
set _CHIPNAME 					"riscv"
set _CPUTAPID 					0x00005c25
set _ESP_ARCH					"riscv"
set _ONLYCPU					1
set _ESP_SMP_TARGET				0
set _ESP_SMP_BREAK 				0
set _ESP_EFUSE_MAC_ADDR_REG  	0x60008844

# Target specific functions should be implemented for each riscv chips.
proc riscv_wdt_disable { } {
    # Halt event can occur during config phase (before "init" is done).
    # Ignore it since mww commands don't work at that time.
    if { [string compare [command mode] config] == 0 } {
        return
    }

    # Timer Group 0 & 1 WDTs
    mww 0x6001f064 0x50D83AA1
    mww 0x6001F048 0
    mww 0x60020064 0x50D83AA1
    mww 0x60020048 0
    # RTC WDT
    mww 0x600080a8 0x50D83AA1
    mww 0x60008090 0
    # SWD
    mww 0x600080b0 0x8F1D312A
    mww 0x600080ac 0x84B00000
}

# This is almost identical with the esp32c2_soc_reset.
# Will be refactored with the other common settings.
proc riscv_soc_reset { } {
	global _RISCV_DMCONTROL

    # This procedure does "digital system reset", i.e. resets
    # all the peripherals except for the RTC block.
    # It is called from reset-assert-post target event callback,
    # after assert_reset procedure was called.
    # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
    # temporarily take it out of reset. Save the dmcontrol state before
    # doing so.
    riscv dmi_write $_RISCV_DMCONTROL 	0x80000001
    # Trigger the reset
    mww 0x60008000 0x9c00a000
    # Workaround for stuck in cpu start during calibration.
    # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
    mww 0x6001F068 0
    # Wait for the reset to happen
    sleep 10
    poll
    # Disable the watchdogs again
    riscv_wdt_disable

    # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
    # We will clean allhalted state by resuming the core.
    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001

    # Put the hart back into reset state. Note that we need to keep haltreq set.
    riscv dmi_write $_RISCV_DMCONTROL 	0x80000003
}

proc riscv_memprot_is_enabled { } {
    # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
    if { [get_mmr_bit 0x600C10A8 0] != 0 } {
        return 1
    }
    # DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
    if { [get_mmr_bit 0x600C10C0 0] != 0 } {
        return 1
    }
    return 0
}

create_esp_target $_ESP_ARCH