04cfc35147
Use the dram cache to save some scans.
2016-09-23 14:16:23 -07:00
dce4a992a3
Single memory reads/writes work.
2016-09-23 14:16:23 -07:00
1b349df638
WIP hackery.
...
Main thing I added is code to output "verilog" for every JTAG op we do,
so we can run the same thing in simulation.
2016-09-23 14:16:23 -07:00
f40862d87c
Go through run-test/idle once per dbus access.
2016-09-23 14:16:23 -07:00
9f22176618
Reading registers appears to work.
2016-09-23 14:16:23 -07:00
84944ded87
Fix up some register stuff.
...
Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
2016-09-23 14:16:23 -07:00
f634702aaf
Successfully determine xlen.
...
There's a nop in there for no reason, though.
2016-09-23 14:16:23 -07:00
db06dd45a0
Improve error checking.
2016-09-23 14:16:23 -07:00
041e0ccf9e
Selecting dbus is sometimes necessary.
2016-09-23 14:16:22 -07:00
25e8b66b08
WIP registers.
2016-09-23 14:16:22 -07:00
3b60c3aa42
Fix bug when waiting for debugint to clear.
2016-09-23 14:16:22 -07:00
67009979ae
Clearer debug logging.
2016-09-23 14:16:22 -07:00
3b3beb04ef
WIP on registers.
2016-09-23 14:16:22 -07:00
482497c51a
Blind implementation of write_memory.
2016-09-23 14:16:22 -07:00
50ca8ac373
Blind implementation of read_memory.
2016-09-23 14:16:22 -07:00
76fe7db0db
In theory assert_reset/deassert_reset work.
2016-09-23 14:16:22 -07:00
ea6836c5f6
WIP, blind coding.
2016-09-23 14:16:22 -07:00
413ab49dfd
Blind coding new dbus behavior.
2016-09-23 14:16:22 -07:00
feff2dd9e7
Always leave the TAP in Run-Test/Idle.
2016-09-23 14:16:22 -07:00
98f2fa897f
Halt should work now.
2016-09-23 14:16:22 -07:00
Tim Newsome