Commit Graph

6 Commits

Author SHA1 Message Date
Jan Matyas e2d3184eba
Fix of DMI batch scans over 64-bits (#432)
This fixes buffer overrun/data corruption during DMI scan batches
on targets with large value of dtmcs.abits > 30 (unusual, but within
the spec).
2020-08-07 08:39:43 -07:00
Greg Savin b7bd3f8d47 BSCAN batch fix (#422)
* fix for batch scans not honoring presence of BSCAN tunnel

* fix formatting to placate checkpatch

* replace DIM with ARRAY_SIZE

* Refactor code that adds a bscan tunneled scan.

* Move bscan tunnel context to the batch structure, and in array
form, one per scan

* adjust code that was inconsistent with project code formatting standards
2019-11-12 09:00:35 -08:00
darius-bluespec 20fc862b15 Perform SBA writes with batch transactions for improved performance. (#405)
* Add riscv_batch_available_scans().

This function will query the number of available scans in a batch.

* Perform SBA writes with batch transactions for improved performance.

Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
2019-09-24 17:49:25 -07:00
Tim Newsome 06445f5743 Propagate error instead of calling abort().
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26 15:04:02 -08:00
Tim Newsome 60354cbea2 clang fix, don't allow unaligned uint64_t pointers 2017-09-18 14:56:46 -07:00
Palmer Dabbelt 8dea2908b7 Add 64-bit and multihart support
This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest draft version of the RISC-V debug spec, as of
   April 26th.  This version fixes a number of spec bugs and should be
   close to the final debug spec.
2017-04-26 09:10:49 -07:00