This allows to merge the implementation in `batch.c` with the one in
`riscv-013.c`.
Change-Id: Ic3821a9ce2d75a7c6e618074679595ddefb14cfc
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Fixes:
- Data types of address & data parameters in riscv_batch_add_*()
and riscv*_fill_dm*() changed to uint64_t and uint32_t.
- Corrected the comparison in riscv_batch_full().
- Corrected assertions in riscv_batch_get_dmi_read_op()
and riscv_batch_get_dmi_read_data().
Cleanup:
- Simplified calloc() fail handling in riscv_batch_alloc().
- Added explicit NULL assignments in riscv_batch_alloc()
for clarity and readability. Don't rely on calloc().
- Removed suffix `_u64` from riscv_*_fill_dm*() since it
does not have any meaning.
- Renamed *dmi_write_u64_bits() to *get_dmi_scan_length()
which better describes its purpose.
Change-Id: Id70e5968528d64b2ee5476f1c00e08459a1e291d
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
The goal of this commit is to provide more robust error handling in
`write_memory_progbuf()`. This is achieved by rewriting it in a fashion
similar to `read_memory_progbuf()`.
The motivation is: some instability in `load_image` was encountered. No
stable reproduction could be obtained, so the root cause was not
determined. Therefore, it was decided to clean-up the code, that may be
implicated in such failures.
Examples of unhanded errors in the code prior to this commit:
* Most of `dmi_write()` return values are discarded.
* If `dm_read()` on `abstractcs` failed (line 4546), `abstractauto` was
not cleared.
Furthermore, the structure of the code was quite complicated, which made
it hard to analyze and reason whether or not all possible failures are
handled properly.
Change-Id: I8a100b686e594855fbf34acf5ccf0e1550f18869
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.
Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
There were a couple of problems with previous implementation:
* Misalligned read would return ERROR_OK and print all zeroes.
* CMDERR_BUSY for abstract access was improperly handled:
According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.
* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.
Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.
riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG scan
operation.
When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.
This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.
Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.
This doubles download speeds to spike using remote bitbang.
Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
* fix for batch scans not honoring presence of BSCAN tunnel
* fix formatting to placate checkpatch
* replace DIM with ARRAY_SIZE
* Refactor code that adds a bscan tunneled scan.
* Move bscan tunnel context to the batch structure, and in array
form, one per scan
* adjust code that was inconsistent with project code formatting standards
* Add riscv_batch_available_scans().
This function will query the number of available scans in a batch.
* Perform SBA writes with batch transactions for improved performance.
Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.
Partly addresses Issue #142
Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports. This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around. The changes are:
* You can pass "-rtos riscv" to the target in OpenOCD's configuration
file, which enables multi-hart mode. This uses OpenOCD's RTOS
support to control all the harts from the debug module using commands
like "info threads" in GDB. This support is still expermental.
* There is support for RV64I, but due to OpenOCD limitations we only
support 32-bit physical addresses. I hope to remedy this by rebasing
onto the latest OpenOCD release, which I've heard should fix this.
* This matches the latest draft version of the RISC-V debug spec, as of
April 26th. This version fixes a number of spec bugs and should be
close to the final debug spec.
Evgeniy Naydanov
Jan Matyas
Mark Zhuang
Erhan Kurubas
Tim Newsome
Jan Matyas
Greg Savin
darius-bluespec
Palmer Dabbelt