Commit Graph

188 Commits

Author SHA1 Message Date
Palmer Dabbelt d2cd725dd3 Invalidate the register cache when touching another hart
The 0.13 code now caches registers interally, so when reading registers
on a diferent hart we need to invalidate the cache.
2018-05-30 17:36:22 -07:00
Palmer Dabbelt 6d9e69499f Don't rely on the RTOS hartid for the register cache 2018-05-30 07:04:14 -07:00
Palmer Dabbelt 06bc6cccd4 Revert "Don't make callbacks from riscv_openocd_{halt,resume}"
This reverts commit bfddd9af64.
2018-05-30 06:26:57 -07:00
Palmer Dabbelt bfddd9af64 Don't make callbacks from riscv_openocd_{halt,resume}
I'm not sure why this would be an issue, but it looks like for some
reason this is causing extraneous halt messages in Eclipse.
2018-05-30 06:20:16 -07:00
Palmer Dabbelt 395592ece3 Revert "Try saving the halted state when examining a target"
This reverts commit f1e8dee522.
2018-05-30 06:00:30 -07:00
Palmer Dabbelt 2ec501a8b3 Revert "double result"
This reverts commit 1b227f1f49.
2018-05-30 06:00:14 -07:00
Palmer Dabbelt 1b227f1f49 double result 2018-05-30 05:56:42 -07:00
Palmer Dabbelt f1e8dee522 Try saving the halted state when examining a target 2018-05-30 05:54:56 -07:00
Palmer Dabbelt ec42c4300e Whoops 2018-05-30 02:25:30 -07:00
Palmer Dabbelt 47731c68d2 If we don't know which thread should be halted then just don't set one 2018-05-30 02:22:59 -07:00
Palmer Dabbelt a7e00a8e72 More debugging 2018-05-30 01:42:20 -07:00
Palmer Dabbelt fccc20ad7a More debug info 2018-05-30 01:29:15 -07:00
Palmer Dabbelt 3c00bd8ff2 Enable debug during the poll 2018-05-30 01:11:17 -07:00
Palmer Dabbelt 0be30cc58c Print a bit more when a hart is halted
I think I'm getting some "wrong hart halted" issues here.
2018-05-30 01:03:02 -07:00
Palmer Dabbelt 755bf8d558 Revert "Don't raise HALT when we're examining a target"
This reverts commit dd382bb6fb.
2018-05-30 00:59:41 -07:00
Palmer Dabbelt a2d118f8e4 Revert "Don't make callbacks from riscv_openocd_{halt,resume}"
This reverts commit fb54cc4fa5.
2018-05-30 00:33:19 -07:00
Palmer Dabbelt dd382bb6fb Don't raise HALT when we're examining a target 2018-05-30 00:29:36 -07:00
Palmer Dabbelt fb54cc4fa5 Don't make callbacks from riscv_openocd_{halt,resume}
I'm not sure why this would be an issue, but it looks like for some
reason this is causing extraneous halt messages in Eclipse.
2018-05-30 00:20:45 -07:00
Palmer Dabbelt 3ce353cafa Revert "Don't make callbacks from riscv_openocd_{halt,resume}"
This reverts commit 43092445df.
2018-05-30 00:05:16 -07:00
Palmer Dabbelt 43092445df Don't make callbacks from riscv_openocd_{halt,resume}
I'm not sure why this would be an issue, but it looks like for some
reason this is causing extraneous halt messages in Eclipse.
2018-05-29 23:34:56 -07:00
Palmer Dabbelt 6b85d0945c Revert "Don't raise HALT when we're examining a target"
This reverts commit b39d196489.
2018-05-29 23:27:41 -07:00
Palmer Dabbelt b39d196489 Don't raise HALT when we're examining a target 2018-05-29 23:18:23 -07:00
Palmer Dabbelt 052b4e3142 Don't print verbose messages when polling
I'm not 100% sure what the right thing to do here is, but I've found
that when I'm not debugging a polling issue there's way too much
verbosity in the debug level as it currently stands.
2018-05-29 19:51:00 -07:00
Tim Newsome ab7ab8a867
Merge pull request #261 from riscv/trigger_enum
Delay trigger enumeration until it's required.
2018-05-25 11:52:10 -07:00
Tim Newsome c3ffbc66e6
Merge pull request #257 from riscv/comment
Comment riscv_set_register, register_write_direct
2018-05-22 14:39:28 -07:00
Tim Newsome b629bbeade Delay trigger enumeration until it's required.
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.

Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22 13:07:25 -07:00
Dan Robertson 0493ff81a1
Fix posible null deref in get_target_type
A null deref occurs if riscv_deinit_target is called and the
target has not been initialized.

Change-Id: Ic34057508ed6686eb48e9fe8220110c42ba2fc5e
2018-05-22 02:57:16 +00:00
Tim Newsome 0ad060d97a Review feedback.
Change-Id: If58c011fc8d89d329d65a6c624ffb631f111cef2
2018-05-17 18:08:08 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Tim Newsome dabaf170ba blank_check_memory prototype has changed.
Just remove our nop implementation. The default behavior when this is
left NULL does the same thing.

Change-Id: I865976c694d24661941584cb0efc92fc26612316
2018-05-08 15:21:49 -07:00
Tim Newsome 2a103bae44 Don't error if hart select isn't implemented.
It's not implemented for 0.11 because we don't need it. Returning error
caused 0.11 targets to not be debuggable since change
848062d0d1.

Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07 15:16:57 -07:00
Tim Newsome 67b4e2c522 counter*h registers only exist on RV32
Fixes #245.

Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-03 12:26:30 -07:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome eeae8c4261 Add gdb_report_register_access_error command
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.

Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
2018-04-02 13:37:53 -07:00
Tim Newsome 3c7c7e26a4
Merge pull request #230 from riscv/deleg
Make m*deleg regs conditional on U/S/N
2018-03-30 14:02:13 -07:00
Tim Newsome 224e7b4f16 Once more... Less sloppy this time.
Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset.
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
Tim Newsome 0c05aafbf8 Fix m*deleg logic.
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00
Tim Newsome b6dca68b2e Make m*deleg regs conditional on U/S/N
Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
2018-03-23 13:43:12 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
Tim Newsome 52eabbd2a5 Add `riscv set_prefer_sba`
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset.
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00
Tim Newsome c10c570dca Fix cut and paste error message.
Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
2018-03-06 13:22:57 -08:00
Tim Newsome ddb894edf6 Add riscv dmi_read/dmi_write commands.
Mostly addresses #207.

Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.

Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
Tim Newsome 1d9418fbb0 Only propagate register errors on some targets
Without this change, connecting to ARM targets is impossible.

Fixes #115.

Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
2018-03-01 15:11:11 -08:00
Tim Newsome 10108b623d Add `authdata_read` and `authdata_write` commands.
They can be used to authenticate to a Debug Module.

There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.

Example usage (very simple challenge-response protocol):
```
init

set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]

reset halt
```

Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
Tim Newsome 3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00