Before this change, when we send an I2C Bulk data at the same
time while Jtag bitbanging functions execute, the microcontroller
puts JTAG bitbanging on wait and executes all I2C bitbanging
function, which causes problems like loss of Ack in DAP responses
and other errors.
With this commit, When I2C interruption occurs, it sets a variable
to true and continues JTAG bitbanging, when it finish it executes
the I2C bitbang.
Change-Id: Ia80bac21f8a259f4a1176b5346bf74ed0aa6e38b
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add GPIO extender initial configuration that is needed to configure
some important GPIOs and ensure that the dev board is ready to work.
Add i2c_write function that make a write transfer to any slave device.
Give a new Product ID to ANGIE to make it different than the non
programmed ANGIE.
Change-Id: I0a8dacb7fe218145b7d3ed1cb75f106ed6256714
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8072
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Give ANGIE a new PID after renumeration to be able to distinguish
the two cases (programmed and not programmed)
Change-Id: I30a91d8ed2e8e261221488b98d40a027ca41da52
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7991
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
We want to keep the tri-state buffers located between the FPGA
and the board, in 'Z' state until we launch an i2c connection.
We launch an i2c start condition, make the SCL
direction 'OUT' to start the i2c protocol and at the end
of the i2c connection at the stop condition, we re-make
the tri-state buffers at 'Z' state.
Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7989
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Change the GPIF state machine, configuring only one of the 4 waveforms
to generate the clock signal (CCLK) used to program the FPGA, and send
one byte every cycle using an 8-bit bus.
Change-Id: I43cf5480b9d5c40cc2f6a62a52ecfe078b76458e
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7976
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
add new i2c bit-banging feature, we can now connect in JTAG with the SoC
target and in i2c with the main board components at the same time.
Change-Id: I8e4516fe1ad5238e0373444f1c3c9bc0814d0f52
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7796
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This is ANGIE's firmware and bitstream code.
The 'Embeded C' code is based on the openULINK project.
The hdl bitstream source code is for the spartan-6 FPGA included in
ANGIE.
Since ANGIE has a different microcontroller (EZ-USB FX2) than openULINK
(EZ-USB AN2131), the registers file (reg_ezusb.h) has been changed
completely, so are the descriptors, interruptions and the endpoints
configuration.
Change-Id: I70590c7c58bac6f1939c5ffba57e87d86850664d
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7701
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Ahmed BOUDJELIDA