Commit Graph

11961 Commits

Author SHA1 Message Date
Tim Newsome 89260a5f1f
Merge pull request #942 from riscv/from_upstream
From upstream
2023-10-27 08:46:43 -07:00
Kirill Radkin b388f4805c OpenOCD memory leak in `hwthread_update_threads()`
Update `os_free()` from `rtos/rtos.c:96` to fix memory leaks

Change-Id: Id7b4c775291b735a0b4423151c2930afce6bf0bd
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7934
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-10-27 11:41:30 +00:00
Tomas Vanek e5d26f1546 flash/nor/spi: add guide to select proper erase cmd
Extend comments in flash_devices array.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I7ab85a2d37803b6bc9fc7a2a91ae2effb6ec288d
Reviewed-on: https://review.openocd.org/c/openocd/+/7925
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2023-10-27 11:41:11 +00:00
Tim Newsome b48636158a
Merge pull request #944 from riscv/remove_extra_kept_alive
Remove an extra call to kept_alive()
2023-10-26 09:18:47 -07:00
Tim Newsome 9500bc4784
Merge pull request #946 from en-sc/en-sc/update-debug-printers
target/riscv: update debug register printers
2023-10-26 09:18:33 -07:00
Evgeniy Naydanov 57b67eda38 target/riscv: update debug register printers
Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-10-25 19:16:36 +03:00
Jan Matyas a26c90f220 Remove an extra call to kept_alive()
This incorrect extra call has been removed in upstream code already
in March 2022, see https://review.openocd.org/c/openocd/+/6836 .

Remove it from riscv-openocd as well.

Change-Id: Ie341f5578c8bfdc518adf1e4bc134919ab76f803
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-25 12:44:01 +02:00
EasyDevKits a080d9795a jtag/drivers: Extension of jtag_libusb_open
In jtag_libusb_open I've added a parameter for delivering the device
description for which this function should search and adjusted all
callers of this function. A new driver for WCH CH347 JTAG chips
will use this new parameter.
See also: https://review.openocd.org/c/openocd/+/7937

Change-Id: I85e1d7b1f7912ba5e223f0f26323ff3b7600e17d
Signed-off-by: EasyDevKits <info@easydevkits.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7938
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-25 01:35:16 +00:00
EasyDevKits 1d555d21d9 tools/scripts: iManufacturer added to camelcase.txt
The iManufacturer is also a member of structure libusb_device_descriptor.
No need to output a check message by checkpatch.sh

Change-Id: Ibbb2eb9cde3482c8d4d6ea784f51a973eb36f8c5
Signed-off-by: EasyDevKits <info@easydevkits.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7936
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-10-25 01:34:28 +00:00
Walter Ji e887cfb9e8 target/mips32: check read regs result in save context
Add result check for mips32_pracc_read_regs in mips32_save_context.

Change-Id: Ie796d2b05a9feb11e246c2d0771b52cad4fb70db
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7932
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-25 01:34:00 +00:00
Walter Ji 18c64af135 target/mips32: rework mips core register related functions
Update mips core definitions.
Reworked mips core register structure and read/write function.
Add coprocessor0 register definitions for target configuration.

Change-Id: I59c1f4cc4020db8a78e8d79f7421b87382fa1709
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7864
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-25 01:33:10 +00:00
Tim Newsome 2d98ef5d13
Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstream
hgatp_mode in riscv_virt2phys_v defined by vsatp value
2023-10-24 07:57:37 -07:00
Tim Newsome 03fff0f86c Fix build.
Change-Id: I20bd0356c63745423e23aec71f272fe2e32db88e
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-23 12:35:45 -07:00
Tim Newsome af08d582b5 Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstream
Conflicts:
	src/flash/nor/drivers.c
	src/target/riscv/riscv.c

Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-23 12:29:21 -07:00
Tim Newsome 132e3faf1d
Merge pull request #940 from riscv/revert-908-disable-soft-bp-size-2-non-compressed
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"
2023-10-23 11:45:50 -07:00
Kirill Radkin 109772012a hgatp_mode in riscv_virt2phys_v defined by vsatp value
Replace `vsatp` with `hgatp` (how it should be)

Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
2023-10-23 18:56:40 +03:00
Tim Newsome 3b0561d081
Merge pull request #935 from riscv/from_upstream
Merge down up to 0384fe5 from upstream.
2023-10-23 08:38:48 -07:00
Tim Newsome 912de786a4
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported" 2023-10-20 15:37:28 -07:00
Tim Newsome aad90d8989
Merge pull request #937 from riscv/cross-build
contrib: Match upstream.
2023-10-18 09:29:56 -07:00
Tim Newsome 0f8f1d1b49
Merge pull request #938 from riscv/stm32lx
flash/stm32lx: Revert to upstream version.
2023-10-18 09:23:04 -07:00
Tim Newsome c0f4991c8d
Merge pull request #936 from riscv/whitespace
Remove end-of-line whitespace.
2023-10-18 09:22:41 -07:00
Tim Newsome 2f71800cbb flash/stm32lx: Revert to upstream version.
Reintroduce checkpatch problem, because now we can handle them better.

Change-Id: Ib81b9910433ae1a240630b898edb19da8d2d5d83
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-17 14:22:17 -07:00
Tim Newsome 9627f548f8 contrib: Match upstream.
Upstream has a checkpatch failure here. I had fixed it because I didn't
know how else to properly get around it back then. Reintroduce the
problem. Now this file is identical to upstream.

Change-Id: Ic03b6bb42945ddbcfd2fe12c0cab5b05eda1a50c
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-17 14:17:09 -07:00
Tim Newsome a495dd854c
Merge pull request #934 from kr-sc/kr-sc/revert-commit
Revert "target: Update messages connected with `examine`"
2023-10-17 09:46:31 -07:00
Kirill Radkin 6c96b9d8c3 Revert "target: Update messages connected with `examine`"
This reverts commit a3db93b1ce.

Reason for revert: https://github.com/riscv/riscv-openocd/pull/931#issuecomment-1761550506
2023-10-17 12:57:39 +03:00
Tim Newsome 46fcba520c Remove end-of-line whitespace.
Change-Id: I0deffafe954abaaa4c593896a2d781c2fa00eef2
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-16 13:48:09 -07:00
Tim Newsome d6060b5d55 Copy snapshot.yml from upstream
At change 0384fe5.

Change-Id: I1081e09f1014c5d240988fc25feba04fc2bb21ef
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-16 12:54:49 -07:00
Tim Newsome 53fcf14d83 Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstream
Conflicts:
      .github/workflows/snapshot.yml
      src/rtos/FreeRTOS.c

Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-16 12:30:06 -07:00
Tim Newsome e1fa78d1b3
Merge pull request #929 from aap-sc/riscv
do not assume DTM version unless dtmcontrol is read successfully
2023-10-16 12:10:25 -07:00
Tim Newsome c8b1d3c91e
Merge pull request #927 from riscv/unavailable_resume
server/gdb_server: Fake resuming unavailable targets.
2023-10-16 08:35:10 -07:00
Parshintsev Anatoly c7d1f0ddab target: check if target is not examined on reg command
Change-Id: I46093c85374986a36d10eaac38b98bd5e05835ca
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7841
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-10-14 12:06:40 +00:00
Tim Newsome 14b1b35e42 server/gdb_server: Log gdb index in debug messages.
This makes it easier to look at log files where multiple gdb instances
are connected.

Change-Id: Ic5aca52b32ee03ac35ffbed9a2fc552abb0a1cba
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7895
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-10-14 12:04:02 +00:00
Marek Vrbka 7822260ed4 target: Change the watchpoint type print from number to letter
Previously, when listing the watchpoints, OpenOCD printed
numbers 0, 1 and 2 representing READ, WRITE and ACCESS type
watchpoints.

This patch changes it to 'r', 'w' and 'a'. This increases the
clarity as what type the watchpoint actually is.

Change-Id: I9eac72dfd0bb2a9596a5b0c080a3f584556ed599
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7909
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-14 12:02:57 +00:00
Marek Vrbka eba5d21193 breakpoints: add rwp all command
This patch adds the "all" option to the rwp command.
It removes all watchpoints, much like rbp all removes
all breakpoints.

Change-Id: Id58dd103085e558f17afa4a287888cf085566ca9
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7907
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14 12:01:38 +00:00
Marek Vrbka 2c8c2cb6b1 command: Prepend logs during command capture
Previously, if you ran a tcl command in capture like so:
"capture { reg 0x1000 hw }"
Such command did overwrite the tcl result if LOG_LVL_INFO or
lower was logged during it.

This patch changes it by prepending the log to the tcl result instead.
As the tcl results should not be lost during capture.

Change-Id: I37381b45e15c931ba2844d65c9d38f6ed2f6e4fd
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7902
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-14 12:00:16 +00:00
Kirill Radkin bcaac692d0 target: Fix an issue with rwp/rbp command in smp targets
If wp/bp is missing at address rwp/rbp won't return zero code (on smp).
Now it fixed.

Fixes: 022e438292 ("target: Change policy of removing watchpoints/breakpoints.")

Change-Id: I3a3c245f7088fc23227b286d2191fc7f3edba702
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7910
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14 11:59:34 +00:00
Florian Fainelli d27a3a00b8 arm_opcode: Add support for ARM MCRR/MRRC
Add support for the ARM MCRR/MRRC instructions which require the use of
two registers to transfer a 64-bit co-processor registers. We are going
to use this in a subsequent patch in order to properly dump 64-bit page
table descriptors that exist on ARMv7A with VMSA extensions.

We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.

Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Michael Chalfant <michael.chalfant@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-14 11:55:42 +00:00
Tim Newsome d454854c13 server/gdb_server: Fake resuming unavailable targets.
When asked to resume an unavailable target, resume any available targets
and report success.

Change-Id: Ieafc63794c1a6eba8948c0f9ce84fa74f9765041
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-13 08:32:19 -07:00
Tim Newsome 6e9514efcd
Merge pull request #926 from riscv/unavailable_events
server/gdb_server: Handle events if first target is unavailable
2023-10-11 13:00:21 -07:00
Tim Newsome 6f4b90afb7
Merge pull request #925 from riscv/unavailable_reg
gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not imple…
2023-10-11 13:00:03 -07:00
Tim Newsome beb705912b
Merge pull request #917 from kr-sc/kr-sc/disable-triggers-option
provide riscv-specific controls to disable triggers from being used for watchpoints
2023-10-11 12:34:07 -07:00
Tim Newsome 41d1ee3715
Merge pull request #931 from kr-sc/kr-sc/update-examine-messages
target: Update messages connected with `examine`
2023-10-11 12:33:38 -07:00
Tim Newsome 52c9ae0aa1 server/gdb_server: Handle events if first target is unavailable
When a target in an SMP group is unavailable, the gdb layer might get an
event for a different target in that SMP group, but not one that is the
primary target for that gdb connection. So propagate events if they're
for any of the targets in the SMP group, not just if it's for the first
one in that group.

Change-Id: I8d6738762acc7c0aef96f56ce2cb7f2eeb233b33
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-10 10:57:30 -07:00
Tim Newsome 969b30326c rtos: Refactor rtos_get_gdb_reg()
Exit early if conditions aren't satisfied, instead of putting the core
code inside an if().

Also return ERROR_FAIL if conditions are satisfied but no matching
registers were found.

Change-Id: I77aa63d9f707bc38d1a71899275ba603914b52c9
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-10 10:51:47 -07:00
Tim Newsome 781a626cf7
Merge pull request #920 from lz-bro/dcsr-cachable
target/riscv: use cacheable read/write function to handle DCSR
2023-10-10 10:21:08 -07:00
Frank Plowman 1bc4182ceb target/nrf52: Create and configure TPIU
Firstly, create the TPIU nrf52.tpiu if using the nrf52 target. This is
standard, using AP 0 and TPIU base address 0xE0040000.
Secondly, add a pre_enable handler for this TPIU which configures the
TRACEMUX field of the TRACECONFIG register. This register is reset
every time the MCU resets, so the pre_enable handler creates a
reset-end handler to ensure the register remains set.

Change-Id: I408b20fc03dc2060c21bad0c21ed713eee55a113
Signed-off-by: Frank Plowman <post@frankplowman.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7901
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-10-07 14:46:52 +00:00
Nishanth Menon 9c7c5ca4eb tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access
While we can read and write from memory from the view of various
processors, all K3 debug systems have a AXI Access port that allows
us to directly access memory from debug interface. This port is
especially useful in the following scenarios:

1. Debug cache related behavior on processors as this provides a
   direct bypass path.
2. Processor has crashed or inaccessible for some reason (low power
   state etc.)
3. Scenarios prior to the processor getting active.
4. Debug MMU or address translation issues (example: TI's Region
   Address Table {RAT} translation table used to physically map
   SoC address space into R5/M4F processor address space)

The AXI-AP port is the same for all processors in TI's K3 family.

To prevent a circular-loop scenario for axi-ap accessing debug memory
with dmem (direct memory access debug), enable this only when dmem is
disabled.

Change-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b
Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7899
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-10-07 14:46:18 +00:00
Nishanth Menon d14fef8495 tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes
The Texas Instruments' K3 devices are a mix of AMP and SMP systems.
The operating systems used on these processors can vary dramatically
as well. Introduce a RTOS array variable, which is keyed off the cpu
to identify which RTOS is used on that CPU. This can be "auto" or
"hwthread" in case of SMP debug etc.

For example:
AM625 with an general purpose M4F running Zephyr and 4 A53s running SMP
Linux could be invoked by:
openocd -c 'set V8_SMP_DEBUG 1' -c 'set RTOS(am625.cpu.gp_mcu) Zephyr' \
	-c "set RTOS(am625.cpu.a53.0) hwthread" -f board/ti_am625evm.cfg

Change-Id: Ib5e59fa2583b3115e5799658afcdd0ee91935e82
Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7898
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-07 14:46:01 +00:00
Dubravko Srsan 7abb93aad4 tcl/target/ti_k3: Add coreid identification to SMP processors
Describe the SMP Armv8 cores in SMP configuration with coreid
explicitly called out. This allows for gdb session to call the smp
behavior clearly.

Change-Id: Ie43be22db64737bbb66181f09d3c83567044f3ac
Signed-off-by: Dubravko Srsan <dubravko.srsan@dolotron.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7897
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-10-07 14:45:11 +00:00
Dubravko Srsan 871276cfea tcl/target/ti_k3: Fix smp target description
When _v8_smp_targets is used with V8_SMP_DEBUG=1, describe the targets
as SMP targets. However, the variable expansion is not in the context of
a proc, and a typo in referring to global $_v8_smp_targets causes this
to fail. Just refer to $_v8_smp_targets directly.

Change-Id: Iffe5fd2703bed6a9c840284285e70b8a8ce84e17
Signed-off-by: Dubravko Srsan <dubravko.srsan@dolotron.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7896
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-10-07 14:44:41 +00:00