Commit Graph

7 Commits

Author SHA1 Message Date
Tomas Vanek ff555afc02 tcl/target, board: remove useless gdb-attach event definitions
Since commit bae76053dc
gdb-attach event is defined as halt by default.
Remove useless and in case of bcm281xx wrong definitions of the event.

Change-Id: I8e69780a93722eb9392673303f54d502e71eceb6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4763
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
2018-11-26 09:31:09 +00:00
Tomas Vanek 1b864d6e49 tcl/target: ti_tms570.cfg restructure dap support
ti_tms570 was probably omitted in commit
2231da8ec4

Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4762
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-11-20 13:06:04 +00:00
Andreas Färber 0c8ec7c826 Fix spelling of ARM Cortex
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.

Cf. http://www.arm.com/products/processors/index.php

Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.

Found via:

  git grep -i "Cortex "
  git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
  git grep -i "CortexM"

Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-20 21:38:03 +01:00
Jiri Kastner 5fa41168dd target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family
from TI datasheets for whole cortex-r4 family added JTAG IDs

TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns192
	0x0B95502F

16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B)
http://www.ti.com/lit/pdf/spns230
	0x0D8A002F
	0x2D8A002F
	0x3D8A002F

RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B)
http://www.ti.com/lit/pdf/spns177
	0x0D8A002F
	0x2D8A002F
	0x3D8A002F

RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns185
	0x0B95502F

RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns176
	0x0B8A002F
	0x2B8A002F
	0x3B8A002F

RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns182
	0x0B95502F

RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns184
	0x0B95502F

TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns186
	0x0B97102F

RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns180
	0x0B97102F

RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/
	0x0B95502F

TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns191
	0x0B95502F

RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns175
	0x0B8A002F
	0x2B8A002F
	0x3B8A002F

TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns165
	0x0B8A002F
	0x2B8A002F
	0x3B8A002F

TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F)
http://www.ti.com/lit/pdf/spns141
	0x0B7B302F

TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B)
http://www.ti.com/lit/pdf/spns164
	0x0B8A002F
	0x2B8A002F
	0x3B8A002F

RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns174
	0x0B8A002F
	0x2B8A002F
	0x3B8A002F

TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B)
http://www.ti.com/lit/pdf/spns162
	0x0B8A002F
	0x2B8A002F
	0x3B8A002F

TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns190
	0x0B95502F

TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns189
	0x0B95502F

TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A)
http://www.ti.com/lit/pdf/spns188
	0x0B95502F

Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Tested-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/2123
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-04-24 14:55:30 +01:00
Alex Ray a1719e0048 TI TMS570 USB Kit board config
Split TMS570 target into LS31/LS21 and LS20/LS10 targets.
Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI.
Tested attaching.

Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620
Signed-off-by: Alex Ray <a@machinaut.com>
Reviewed-on: http://openocd.zylin.com/2089
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-04-24 14:55:16 +01:00
Seth LaForge 3427cf2b7e cortex_a: fix endiannes issues on TI TMS570
The TI TMS470 and TMS570 series of processors are BE-32 processors,
despite BE-32 not being supported by ARM in the Cortex-R4 core. TI
hacked in BE-32 support, which requires odd swizzling in OpenOCD to
make memory reads and writes function correctly. In particular,
without this change, OpenOCD word reads and writes had the bytes
reversed, and halfword and byte packed reads were reading garbage.
In my testing, this change fixes these problems.

Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/2064
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-04-14 18:20:36 +00:00
Andrey Yurovsky 6accbb8baa add TI TMS570 support scripts
Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick
development kit, TMDX570LS31USB.  Tested attaching, reset/halt/run, and
reading and writing memory and registers.

Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1788
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-11-06 13:06:41 +00:00