interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,854 Commits 65 Branches 14 Tags 104 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Mathias K 0f1d00bda6 Change reset configuration. 
This patch change the default reset config from SYSRESETREQ to the working
VECTRESET.

Change-Id: I21a9a74b9c0c68cfa3a6e6dac9b123acc98a93cb
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/1186
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
 2013-03-05 15:09:23 +00:00
Spencer Oliver 2ce4e31bbc cfg: update for target's that support cortex_m AIRCR SYSRESETREQ 
If the target supports SYSRESETREQ make sure we use that as the default
if srst is not fitted/configured.

Change-Id: I24c907493134506320e69c1218702930629c1cdc
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/792
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
 2012-08-29 06:24:36 +00:00
Jim Norris 0ab3f83667 Add new configuration files for the Diolan LPC-4350-DB1 development 
board with the NXP LPC4350 processor.

Change-Id: I0843e96af9ca05d3e598e2e16eb19fc0581ab46d
Signed-off-by: Jim Norris <u17263@att.net>
Reviewed-on: http://openocd.zylin.com/501
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
 2012-03-06 13:31:59 +00:00