riscv-openocd

Commit Graph

Author	SHA1	Message	Date
Bohdan Tymkiv	4440bf1fcd	psoc6: Run flash algorithm asynchronously to improve performance Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin \| w/o this change \| with this change \| ----------------------------------\|-----------------\|------------------\| KitProg2/CMSIS-DAP, SWD @ 1 MHz \| 4 KiB/s \| 10 KiB/s \| J-Link Ultra, SWD @ 1 MHz \| 17 KiB/s \| 31 KiB/s \| J-Link Ultra, SWD @ 4 MHz \| 33 KiB/s \| 57 KiB/s \| Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>	2018-04-23 20:42:06 +01:00
Tomas Vanek	7690a74b09	flash/nor: implement flash bank deallocation in drivers with simple alloc All drivers which simply allocate one driver_priv memory block per each bank now use default_flash_free_driver_priv() Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4417 Tested-by: jenkins Reviewed-by: Liviu Dudau <liviu@dudau.co.uk> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>	2018-04-04 20:14:18 +01:00
Bohdan Tymkiv	e9f54db003	Add support for Cypress PSoC6 family of devices * Tested on CY8CKIT-001 kit with PSoC6 daughter board. * Tested with several J-Link adapters (Ultra+, Basic) Change-Id: I0a818c231e5f0b270c7774037b38d23221d59417 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4233 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>	2018-02-14 08:27:30 +00:00

Author

SHA1

Message

Date

Bohdan Tymkiv

4440bf1fcd

psoc6: Run flash algorithm asynchronously to improve performance

Existing psoc6 driver starts flash algorithm for each Flash row. This is
suboptimal from performance point of view, starting/stopping flash
algorithm for each row adds significant overhead. This change starts
flash algorithm and leaves it running asynchronously while driver
performs flash operations.

Performance gain is 170...250% depending on probe:

flash write_image img_256k.bin    | w/o this change | with this change |
----------------------------------|-----------------|------------------|
KitProg2/CMSIS-DAP, SWD @ 1 MHz   |     4 KiB/s     |     10 KiB/s     |
J-Link Ultra, SWD @ 1 MHz         |    17 KiB/s     |     31 KiB/s     |
J-Link Ultra, SWD @ 4 MHz         |    33 KiB/s     |     57 KiB/s     |

Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4472
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

2018-04-23 20:42:06 +01:00

Tomas Vanek

7690a74b09

flash/nor: implement flash bank deallocation in drivers with simple alloc

All drivers which simply allocate one driver_priv memory block
per each bank now use default_flash_free_driver_priv()

Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4417
Tested-by: jenkins
Reviewed-by: Liviu Dudau <liviu@dudau.co.uk>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

2018-04-04 20:14:18 +01:00

Bohdan Tymkiv

e9f54db003

Add support for Cypress PSoC6 family of devices

* Tested on CY8CKIT-001 kit with PSoC6 daughter board.
* Tested with several J-Link adapters (Ultra+, Basic)

Change-Id: I0a818c231e5f0b270c7774037b38d23221d59417
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

2018-02-14 08:27:30 +00:00

3 Commits