Commit Graph

4915 Commits

Author SHA1 Message Date
Marek Vrbka 1c6b7fa2c9 target: Fix force-reading of registers and add flush capability
1) OpenOCD has the capability to 'force' a register read from the
target. This functionality however silently breaks the register
cache: During 'get_reg force' or 'reg <name> force',
reg->type->get() is called which will silently overwrite
dirty items in the register cache, causing a loss of unwritten
register values. This patch fixes that by adding a flush
callback for registers, and by using it when it is needed.

2) The register write commands did not have the 'force' flag;
this was present for register read commands only.
This patch adds it.

3) This patch also introduces the flush_reg_cache command. It
flushes all registers and can optionally invalidates the register
cache after the flush.

For targets which implement the register cache should implement
the flush() callback in struct reg_arch_type.

This functionality is also useful for test purposes. Example:
 - In RISC-V, some registers are WARL (write any read legal)
   and this command allows to check this behavior.

We plan to implement the corresponding callback
in the RISC-V target.

Change-Id: I9537a5f05b46330f70aad17f77b2b80dedad068a
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2024-12-20 14:56:56 +03:00
Evgeniy Naydanov 4b9fb1972f Merge up to 133dd9d669 from upstream
Change-Id: Iaaf234da839cbed61684f4615135c9a42213c56a
2024-12-18 12:41:19 +03:00
Evgeniy Naydanov cf9963ad81
Merge pull request #1181 from en-sc/en-sc/reg-invalidate
target/riscv: clean-up register invalidation
2024-12-11 16:40:20 +03:00
Evgeniy Naydanov de20c2ad5f target/riscv: clean-up register invalidation
* Registers were not invalidated if the hart became unavailable.
* Improved logging in the case register invalidation involves loss of
  information.

Change-Id: Icfb5e190dd6dcb1a97e4d314d802466cab7a01e4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-12-10 15:25:22 +03:00
Farid Khaydari d5c2604418 target/riscv: replaced repeating ternary operator with variable
Replaced repeating ternary operator with variable

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-12-10 13:40:08 +03:00
Farid Khaydari 4dcd80164a target/riscv: use buf_get_uXX instead of manual bit shift
Replaced manual bit shift with buf_get_u64/buf_get_u32

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-12-04 22:56:05 +03:00
Anatoly Parshintsev c430c24330
Merge pull request #1167 from fk-sc/fk-sc/rwargs
target/riscv: pass memory access info in struct, move write_memory pointer
2024-12-04 21:04:56 +03:00
Anatoly Parshintsev ca80920157
Merge pull request #1176 from aap-sc/aap-sc/csr_as_hex_regression_fixup
fix incorrect parsing of names for custom csr registers
2024-11-29 18:26:19 +03:00
Farid Khaydari eb4e717a3b target/riscv: pass memory access info in struct, move write_memory pointer
This changes will allow to unite read_memory/write_memory fucntions
to one access function

(1) Replaced read/write functions arguments with one structure
(2) Unified read_memory/write_memory function pointers
    to be stored in same structure

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-11-29 18:12:53 +03:00
Anatoly Parshintsev 0f0302b029
Merge pull request #1174 from fk-sc/fk-sc/checker-fix
target/riscv: fix memory access result type checker function return in case of assertion
2024-11-29 01:23:37 +03:00
Parshintsev Anatoly 109646c09d fix incorrect parsing of names for custom csr registers
this commit fixes a regression introduced in
ba8c1eef5a.

The regression was caused by removal of these lines:

```
-                       /* Register prefix: "csr_" or "custom_" */
-                       strcpy(name, reg_type);
-                       name[strlen(reg_type)] = '_';
```

causing all CSR names with custom names to be parsed as empty strings.
2024-11-27 22:08:20 +03:00
Evgeniy Naydanov eb1ecd7d10
Merge pull request #1170 from fk-sc/fk-sc/priv-mod
target/riscv: decrease modify_privilege function nesting level
2024-11-26 17:26:49 +03:00
Farid Khaydari c8ae081979 target/riscv: fix memory access result type checker function return in case of assertion
Fix memory access result type checker return in case of assertion

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-11-26 12:56:36 +03:00
Anatoly Parshintsev 658766858d
Merge pull request #1162 from aap-sc/aap-sc/csr_as_hex
target/riscv: allow hexadecimal values to expose_csr-like commands
2024-11-25 23:00:32 +03:00
Henrik Mau 133dd9d669 target/xtensa: add maskisr command support for NX
Add maskisr command support to Xtensa NX targets allowing masking
of interrupts during single stepping.

Change-Id: I3835479de8015f1a2842afd1aeab24829e385031
Signed-off-by: Henrik Mau <henrik.mau@analog.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8575
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2024-11-23 13:54:44 +00:00
Marc Schink 76e228f733 target/cortex_m: Use LOG_TARGET_xxx()
Use LOG_TARGET_xxx() for the remaining log messages.

Change-Id: If52e3935b57e4c39212ce6b5111ff65159de1373
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8580
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-11-23 13:54:03 +00:00
Marc Schink c837beaf5d target/breakpoints: Use LOG_TARGET_ERROR()
Use LOG_TARGET_xxx() for the remaining log messages.

Change-Id: I4b86b206d17dead0662388e827204b40a7d29edd
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8579
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-11-23 13:53:42 +00:00
Marc Schink f5036aff3a target/xtensa: Remove 'ERROR: ' prefix in error log
Remove the prefix since it is redundant.

Change-Id: I9c23c0479ba40be24e471309e720060cd03763ee
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8577
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-11-23 13:52:56 +00:00
Marc Schink 8c739a45a0 helper/jim-nvp.h: Rework 'isconfigure' variable
Change the variable name to 'is_configure' to be compatible with the
coding style and use 'bool' as data type.

Change-Id: I8609f9807c8bd14eaf6c93acf63fd51b55c9bbbb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8573
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-11-23 13:48:52 +00:00
Antonio Borneo 61fbcbeca8 semihosting: make local functions static
The functions:
- semihosting_opcode_to_str();
- semihosting_write_fields();
- semihosting_set_field();
are not referenced outside the file.

Make them static.

Change-Id: Ia8d35554673145fdfe0e501543eb18919863039f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8551
Tested-by: jenkins
2024-11-23 13:48:25 +00:00
Antonio Borneo b04a58e3fc target: esirisc: make local functions static
The function esirisc_jtag_get_eid() is not used outside the file.
Make it static.

The function esirisc_jtag_disable_debug() is never used.
Make it static and mark it as unused.

Change-Id: I5c99cbf77cc9c527b6e18a3f67caa24f8551d09c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8550
Tested-by: jenkins
2024-11-23 13:48:12 +00:00
Antonio Borneo df42faf51d target: aarch64: drop unused armv8_mmu_translate_va()
The function is not used.
Drop it!

Change-Id: I1625e03714b5a842f668098191c39cce34f815e8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8549
Tested-by: jenkins
2024-11-23 13:47:55 +00:00
Antonio Borneo c5babec794 target: x86_32: make x86_32_common_read_io() static
The function is not referenced outside the file.
Make it static.

Change-Id: Ic2552c040b6b46c0334851a4fc0fdaa400e11e4c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8548
Tested-by: jenkins
2024-11-23 13:47:33 +00:00
Antonio Borneo f3aeb3d676 target: dsp563xx: make dsp563xx_once_reg_read_ex() static
The function is not referenced outside the file.
Make it static.

Change-Id: Ifeccc5e38f3da4b4111422860bc1c1447d00f7fe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8547
Tested-by: jenkins
2024-11-23 13:47:15 +00:00
Evgeniy Naydanov 1bf7efb2d5
Merge pull request #1144 from sunnyzhu-learning/resume-before-step-develop
target/riscv:Perform single step before resume if necessary
2024-11-21 12:37:59 +03:00
Farid Khaydari 8b7013028c target/riscv: decrease modify_privilege function nesting level
Restructured modify_privilege function to decrease nesting level

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-11-21 00:04:15 +03:00
Parshintsev Anatoly ba8c1eef5a target/riscv: allow hexadecimal values to expose_csr-like commands
hexadecimal values are often used in the documentation. Forcing user to
convert CSRs addresses to decimal is unnecessary.
2024-11-19 22:28:57 +03:00
Evgeniy Naydanov f51900b4a2
Merge pull request #1165 from aap-sc/aap-sc/resume_debug_errors
target/riscv: detailed error messages for cases when resume operation fails
2024-11-18 13:17:25 +03:00
Evgeniy Naydanov 463d1b0866
Merge pull request #1157 from zqb-all/support-disable-auto-fence
target/riscv: support disable auto fence
2024-11-18 13:16:54 +03:00
Evgeniy Naydanov c53f9319c8
Merge pull request #1163 from en-sc/en-sc/from_upstream
Merge up to fd62626dff from  upstream
2024-11-18 13:16:18 +03:00
Evgeniy Naydanov a2f5da3289
Merge pull request #1161 from en-sc/en-sc/deassert-reset
target/riscv: avoid updating `target` if `ackhavereset` fails
2024-11-14 13:23:42 +03:00
Parshintsev Anatoly faffae0493 target/riscv: detailed error messages for cases when resume operation fails
This change aims to provide more context in case if resume operation
fails. Before the change messages were quite confusing.
2024-11-14 12:23:47 +03:00
Evgeniy Naydanov f7ea8245e6
Merge pull request #1160 from zqb-all/reduce-log
[NFC] target/riscv: remove LOG_ERROR when COMMAND check ARGC fail
2024-11-12 17:45:57 +03:00
Evgeniy Naydanov cabb6000df Merge up to fd62626dff from upstream
Conflicts are related to `unsigned`->`unisgned int` cleanup:
* `src/jtag/drivers/ftdi.c` -- between
  6749c70a3a and
  a64dc23bf1.
* `src/rtos/hwthread.c` -- between
  ef3e61bebc and
  436e6f1770.
* `src/target/target.c` and `.h` -- between
  53ec10b61d and
  e72733d590.
* `src/target/riscv/*` -- due to
  957eb741a0 and
  fec3b22421.
  Resolved by:
    * Changing the return type of `riscv_batch_get_dmi_read_op()` to
      `uint32_t`.
    * Using RISC-V OpenOCD's version in other cases.

Change-Id: Ia6e2129c6fddb1dec26adcd936506af2539412ef
2024-11-12 17:25:33 +03:00
Evgeniy Naydanov fd62626dff target/breakpoints: fix types in `watchpoint_add_internal()`
There was a conflict:
1. commit 2cd8ebf44d ("breakpoints: use 64-bit type for watchpoint mask
   and value")
2. commit 0bf3373e80 ("target/breakpoints: Use 'unsigned int' for
   length")

The second commit was created erlier, but merged later so the types of
`mask` and `value` became `uint32_t` in `watchpoint_add_internal()`.

This created a bug:
`WATCHPOINT_IGNORE_DATA_VALUE_MASK` is defined as `(~(uint64_t)0)`.
Truncation to uint32_t makes it so the comparisons with the constant
don't work.

Change-Id: I19c414c351f52aff72a60330d83c29db7bbca375
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8500
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Karl Palsson <karlp@tweak.au>
2024-11-11 17:33:56 +00:00
zhusonghe 215ecdaedf target/riscv:Perform single step before resume if necessary
Two cases where single step is needed before resume:
1. ebreak used in software breakpoint;
2. a trigger that is taken just before the instruction
   that triggered it is retired.

Signed-off-by: Songhe Zhu <zhusonghe@eswincomputing.com> Co-developed-by: Fei Gao <gaofei@eswincomputing.com> Co-developed-by: xiatianyi <xiatianyi@eswincomputing.com>
2024-11-11 15:31:49 +08:00
Evgeniy Naydanov 784687d781 target/riscv: avoid updating `target` if `ackhavereset` fails
`target`'s `state` and `debug_reason` should not be updated in
`deassert_reset` if sending reset acknowledgment fails.

Change-Id: I86136fe829e7a7c6b69f718f0cf32322e40341b0
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-11-08 16:36:25 +03:00
Mark Zhuang e024f112e3 [NFC] target/riscv: remove LOG_ERROR when COMMAND check ARGC fail
Per current OpenOCD conventions, LOG_ERROR should not be printed
when ERROR_COMMAND_SYNTAX_ERROR is returned. OpenOCD will print
the command syntax to the user on its own.
2024-11-06 19:32:20 +08:00
Mark Zhuang 340e38a9ed target/riscv: support disable auto fence
Support disable automatic fence, it's useful for
debug some cache related issue.
2024-11-06 17:15:57 +08:00
Mark Zhuang 134e56338d target: riscv: convert 'unsigned' to 'unsigned int'
Change-Id: I10b9abf9e42389eb91b210b8c2f01219ca9068cd
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8366
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-11-02 21:02:42 +00:00
Antonio Borneo 3ce0962f2c target: cortex_m: fix polling for target kept under reset
In multi-target SoC not all the targets are running simultaneously
and some target could be powered off or kept under reset.
Commit 4892e32294 ("target/cortex_m: allow poll quickly get out
of TARGET_RESET state") does not considers the case of a target
that is kept in reset and expects the target to change state from
TARGET_RESET immediately.
This causes OpenOCD to log continuously:
	Info : [stm32mp15x.cm4] external reset detected
	Info : [stm32mp15x.cm4] external reset detected
	Info : [stm32mp15x.cm4] external reset detected

Read again dhcsr to detect the 'stable' reset status and quit,
waiting for next poll to re-check the target's status.

Change-Id: Ic66029b988404a1599bb99bc66d4a8845b8b02c6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 4892e32294 ("target/cortex_m: allow poll quickly get out of TARGET_RESET state")
Reviewed-on: https://review.openocd.org/c/openocd/+/8399
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2024-11-02 20:59:48 +00:00
Evgeniy Naydanov f9a1292716
Merge pull request #1154 from en-sc/en-sc/dcsr-ebreak-halt-on-reset
target/riscv: avoid unnecessary `dcsr.ebreak*` update on reset
2024-10-30 17:52:56 +03:00
Mark Zhuang b7708c84e6 [NFC] target/riscv: simplify code with MAX macros
slightly improves readability
2024-10-28 22:57:07 +08:00
Evgeniy Naydanov 9ff272e34b
Merge pull request #1149 from zqb-all/read-write-cross-page
riscv: fix read/write virtual memory across page boundaries
2024-10-28 14:40:13 +03:00
Evgeniy Naydanov 3fe20e7aa4 target/riscv: avoid unnecessary `dcsr.ebreak*` update on reset
There is no need to change if `dcsr.ebreak*` fields after a reset if a
user requested a configuration that will result `dcsr.ebreak*` field
values equal to reset values.

Change-Id: I2844d30aef8f735c7b37394ee422e9b3f04a2e3b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-10-25 17:27:19 +03:00
Mark Zhuang 92d7a5798d [NFC] target/riscv: refactor riscv_read_memory,riscv_write_memory
Reduce duplicate code
2024-10-24 23:47:58 +08:00
Mark Zhuang 4a1bd80842 target/riscv: fix cross-page misaligned access when mmu not enabled
When mmu is disabled, simply call the physical read/write function
2024-10-24 23:47:48 +08:00
Mark Zhuang 593b377073 target/riscv: fix read/write virtual memory across page boundaries
When read/write virtual addresses cross page boundaries,
the physical addresses are not necessarily contiguous and
need to call virt2phys again.
2024-10-24 23:39:10 +08:00
Evgeniy Naydanov 7b4ad6f173
Merge pull request #1152 from fk-sc/translation-drivers
target/riscv: added translation drivers
2024-10-24 15:06:27 +03:00
Farid Khaydari 6a27d9fbc0 target/riscv: added translation drivers
Existing flags: 'enable_virtual' and 'enable_virt2phys' were
replaced with explicit translation drivers. Motivation:

(1) Having 'enable_virtual' and 'enable_virt2phys' flags set simultaneously
may cause double address translation which is unacceptable

(2) Flags were global for all targets which is wrong too

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-10-23 12:36:29 +03:00