Commit Graph

8677 Commits

Author SHA1 Message Date
Oleksij Rempel e195b0bc81 armv7a: forward error value in armv7a_cache_auto_flush_all_data
if armv7a_l1_d_cache_clean_inval_all will fail, error value is never
forwarded. So make sure we do it from now.

Change-Id: I02acfaa938ec09f58df77191d13d8f4bb3308720
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4384
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-21 08:19:19 +00:00
Tim Newsome 3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
Kaspar Schleiser d570f89303 target/riscv: add some switch fallthrough comments 2018-02-20 14:31:31 +01:00
Tim Newsome 6b02ab4196 Fix build with --disable-target64
Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
2018-02-19 15:07:10 -08:00
Tim Newsome cf895486b6 Add a build with --disable_target64
Change-Id: Ibe52a678ab7b8145ffaa54dce38149aa95bdb48c
2018-02-19 14:25:48 -08:00
Tim Newsome 352e6b82ed
Merge pull request #208 from riscv/run_from_trigger
Handle resuming from a trigger...
2018-02-19 13:42:50 -08:00
Jonas Norling 6d390e1b2a efm32: Refactor EFM32 chip family data, add more chips
Add support for more EFM32/EFR32 Series 1 families. The family IDs
come from the DEVICE_FAMILY list in the EFM32GG11 reference manual,
which is the most up to date source I could find. Register locations
have been checked against SiLab's header files.

No datasheets or headers were available for EFR32MG2, EFR32xG14 and
EFM32TG11B, so they are just assumed to follow the pattern. EFM32GG11B
has the MSC registers on a different address compared to other chips.

This commit attempts not to change current behavior when detecting
chips. One detail that has changed is that PAGE_SIZE is read before
applying the workaround for old Giant and Leopard Gecko revisions, but
this is believed to be OK because the register exists but just has an
invalid value in it.

The manuals disagree on which of 120 and 121 is WG, so this commit
leaves it as is.

Change-Id: Ia152b0b9e323defc5158cb02d9a6b04a27008f2a
Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-on: http://openocd.zylin.com/4263
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
2018-02-14 08:27:57 +00:00
Bohdan Tymkiv e9f54db003 Add support for Cypress PSoC6 family of devices
* Tested on CY8CKIT-001 kit with PSoC6 daughter board.
* Tested with several J-Link adapters (Ultra+, Basic)

Change-Id: I0a818c231e5f0b270c7774037b38d23221d59417
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4233
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-14 08:27:30 +00:00
Andreas Bolsch 445dc23eb5 Handle improperly build image files gracefully
Images build improperly (by simply concatenating separate images) were accepted,
but anything after the first end-of-file record *silently* ignored. Now emit warning
for intel and motorola images upon non-whitespace after first end-of-file record but
continue reading anyway.
ST ships some images broken that way in their CubeMX packages ...

Change-Id: I0c5d08fa90070fed11fb805c5f0dc39817048176
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4281
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-14 08:27:01 +00:00
Tomas Vanek 38030e0115 psoc4: update for 4x00BLE, L, M, S and PRoC BLE devices
Flash ROM API command PSOC4_CMD_SET_IMO48 is now optional on new devices.
Also code tidy up:
- improved system ROM call error detection
- probe does not require the target to be halted
- default_padded_value and erased_value set to 0
- fixed endianess problem in flash write and protection setting
- removed fancy chip detection table as it would be updated too often
- psoc4 flash_autoerase is now on by default to ease programming

psoc4.cfg distinguishes chip family and uses either proprietary acquire
function of a KitProg adapter or TEST_MODE workaround to "reset halt"

Change-Id: I2c75ec46ed0a95e09274fad70b62d6eed7b9ecdf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3807
Tested-by: jenkins
Reviewed-by: David Girault <david.f.girault@gmail.com>
2018-02-14 08:26:40 +00:00
Tomas Vanek 5830bf09a7 flash/nor/at91samd: add SAM R30 family
Microchip SAM R30 consist of a MCU SAM L21 and a radio.
Similarly SAM R21 = SAM D21 + radio. Therefore SAM R devices
was incorporated into SAM D21 and L21 device groups.

Change-Id: I3448d784cae888070b57c2f504583760ddffc97f
Suggested-by: Martin Deicke <martin.deicke@an-solutions.de>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4282
Tested-by: jenkins
2018-02-14 08:26:14 +00:00
Megan Wachs 1b37f60969 riscv-compliance: Check that DPC is sign extended properly. 2018-02-13 15:02:31 -08:00
Megan Wachs 8f7195af76 riscv-compliance: Turn off ABSTRACTAUTO until the appropriate time 2018-02-13 13:47:14 -08:00
Megan Wachs 313885cb3b riscv-compliance: whitespace fixes 2018-02-13 13:08:15 -08:00
Megan Wachs 2e525e391f riscv-compliance: get it compiling against riscv branch again 2018-02-13 13:01:56 -08:00
Megan Wachs 88370b3989 riscv-compliance: fix some macros which were renamed 2018-02-13 11:44:53 -08:00
Megan Wachs 41efb5b964 riscv-compliance: Fix libjaylink version 2018-02-13 11:03:52 -08:00
Megan Wachs f3bce93dc8 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-13 10:57:32 -08:00
Tim Newsome 6cbb45f7f1
Merge pull request #205 from riscv/update
Merge changes from upstream.
2018-02-08 11:36:11 -08:00
Gleb Gagarin 2e415b3930
Merge pull request #210 from riscv/reset_before_hart_enum
complete reset before writing to hartsel field
2018-02-07 18:35:06 -08:00
Gleb Gagarin 5c543ee3a1 complete reset before writing to hartsel field 2018-02-07 16:06:02 -08:00
Tim Newsome ace6b7e49a Handle resuming from a trigger...
... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.

Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
2018-02-07 13:30:23 -08:00
Matthias Welwarsky 78a4b6607e cortex_a: faster debug init
Don't use atomic dap operations when not necessary

Change-Id: Idc6dcd2bda95f7994852df4ae2a588976f4c9010
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4142
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-07 18:10:52 +00:00
Megan Wachs 5cf705d360 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-06 10:26:22 -08:00
Tomas Vanek 0056037d68 flash/nor/kinetis_ke: fix warning retval set but not used
I see no reason for not returning error from target_run_algorithm()
to higher level.

Reported by Clang static analyzer.

Change-Id: Iaaa8b66e487ecae88c0cf4ae2addba63341c032c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4391
Tested-by: jenkins
Reviewed-by: Ivan Meleca <ivan@artekit.eu>
2018-02-04 21:44:27 +00:00
Paul Fertser f2b228f5d1 jtag: drivers: stlink: ignore write verify error
This looks like some inappropriate stlink (mis-)feature and it messes
operations for writing to certain memory-mapped registers.

Discussed at https://forum.sparkfun.com/viewtopic.php?f=18&t=44949 .
Also known to be problematic for working with Kinetis parts.

Reported by robertfoss_ on IRC.

Change-Id: I8633aed13346c596000ba6c377758e1bb96db73f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4368
Tested-by: jenkins
Reviewed-by: Robert Foss <robert.foss@memcpy.io>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2018-02-03 15:33:56 +00:00
Tim Newsome 706af27eee Merge branch 'master' into update
Change-Id: I2cd34ed5bb1903736ae8ce109acebaf13bf49805
2018-02-02 14:17:32 -08:00
Tim Newsome 6e278cded6
Merge pull request #199 from riscv/regname
Mention register name instead of number in error
2018-02-01 12:05:33 -08:00
Tomas Vanek c2b2a7a3b8 Kinetis_ke: add KEAx family to texi and cfg comment
Change-Id: Id8f676b027f57fc540473c1a3a01bdd2ec49a200
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4232
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
2018-02-01 19:38:49 +00:00
Tim Newsome a80ab87efd Add unreachable return for mingw build.
Change-Id: I8c0c4d7be8f6f28638cc2b5ae8114f5c8f95f94b
2018-01-31 16:55:43 -08:00
Tim Newsome 7114ef485c Fix cut and paste bug.
Change-Id: I1c554cbe3d7cb7845bc62f14ae6b8dff107eb192
2018-01-31 16:45:33 -08:00
Tim Newsome bb2c25c5ce Make OpenOCD work when there is no program buffer.
Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.

Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
2018-01-31 15:33:45 -08:00
Tim Newsome 6f0d70f5c8 Mention register name instead of number in error
Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
2018-01-30 12:30:39 -08:00
Tim Newsome ee93a9b2f1 Add error handling code to system bus read/write
It's not tested because spike never reports any busy errors since every
access happens instantaneously.

Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
2018-01-30 08:53:46 -08:00
Paul Fertser 5a98ff786e tcl: interface: harmonise RPi configs
Make all configs specify same JTAG and SWD GPIO numbers.

Change-Id: I65b09c1671c97f253f0aab88e511de7409d91e0a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3932
Tested-by: jenkins
2018-01-30 07:39:24 +00:00
Paul Fertser 3c9bd7c6f3 flash: nor: jtagspi: fix jtagspi_read_status() warning
Clang static analyzer says that in certain cases "Assigned value is
garbage or undefined" there.

Change-Id: Ib35a4cf7a553ba9461270a0dc4c4b9b205091e73
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4338
Tested-by: jenkins
2018-01-30 07:36:51 +00:00
Paul Fertser ab597027ea doxygen: fix issues with recent Doxygen versions
This fixes parsing of several documentation files which do not have
dot in the filename.

style.txt change fixes doxygen warnings and ensures proper display of
comment begin/end instructions in HTML.

Tested with Doxygen 1.8.13.

Change-Id: I9fd9ac3b51b47076b8fdbd3e93b90c3eba9b9631
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4342
Tested-by: jenkins
2018-01-30 07:35:50 +00:00
Paul Fertser fa86553e76 x86_32_common: fix some warnings
Mostly "Dead assignment" reported by Clang static analyzer.

Change-Id: Ibf81d2ba2462570ee3a40e57a60c55a1d1fa0c00
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4351
Tested-by: jenkins
2018-01-30 07:34:32 +00:00
Tim Newsome 0f0c5b1ff5 Merge branch 'riscv' into sysbusbits
Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
2018-01-29 11:39:14 -08:00
Tim Newsome ec543bdc7b
Merge pull request #198 from riscv/hartsellen
Detect hartsellen, limiting which harts we probe
2018-01-29 11:11:00 -08:00
Tomas Vanek dd890d4cad arm_adi_v5: fix return value of mem_ap_read/write for size 0
Unhandled marginal case produced a warning in Clang static analyzer.

Change-Id: I3e2fc4182fa4f863acfb972b1e7a512fce5bf33a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/4357
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-29 14:47:40 +00:00
Matthias Welwarsky 1ac0f5d493 aarch64: clean up scan-build errors
scan-build reported a couple of problems with code in aarch64.c,
this patch cleans them up. No functional changes.

Change-Id: Ie210237ddc840a8bbcd535f86a3a5faf473132f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4346
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-29 08:24:17 +00:00
Paul Fertser e60573c528 jtag: drivers: usb_blaster: clarify lowlevel driver selection code
This patch should make the code logic more transparent and user
notifications more useful.

It also fixes a warning "array subscript is below array bounds" that
leads to FTBFS on Raspbian GNU/Linux 8 (jessie).

Change-Id: I626b6a5bc013dfee7d36cf196f0abab981d30675
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3931
Tested-by: jenkins
2018-01-27 17:16:02 +00:00
Tim Newsome 6a98fb7076 Detect hartsellen, limiting which harts we probe
Tested with doctored spike with hartsellens of 0, 1, 3, and 10.

Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
2018-01-26 16:39:58 -08:00
Tim Newsome 5184c32125 Clear errors that we see.
Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...

Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
2018-01-26 15:43:05 -08:00
Tim Newsome b67379700b Add support for v1 system bus access.
This is functional, but doesn't handle errors.

Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
2018-01-26 15:43:05 -08:00
Tim Newsome beac00149c Use new debug_defines.h
Change-Id: Iefc8424343dbed05fa9dacc626829955fc16f299
2018-01-26 15:41:45 -08:00
Daniel Kucera a0c4c9e717 nor/nrf5: added nrf51822 QFAAH2
Change-Id: I59725e098371c63ec3e6aa1d91bfed36b824a182
Signed-off-by: Daniel Kucera <daniel.kucera@gmail.com>
Reviewed-on: http://openocd.zylin.com/4334
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-26 22:38:27 +00:00
Matthias Welwarsky a640f139ba aarch64: implement mmu on/off for aarch32
add decoding of aarch32 core modes (register layout is compatible)

Change-Id: I34c3146a7b1f836d3006be2b76b036da055b3d3e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4374
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-26 10:53:09 +00:00
Tim Newsome 68c57474f9
Merge pull request #192 from riscv/memlog
Make all memory logging lines consistent.
2018-01-25 10:51:35 -08:00