Fix cut and paste error in docs. (#352)

Fixes #349.

Change-Id: I5cfd5b28eef463cfa1faa3d1d766eb3e3f52904a
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Tim Newsome 2019-02-14 12:53:28 -08:00 committed by GitHub
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@ -9117,7 +9117,7 @@ command can be used if OpenOCD gets this wrong, or a target implements custom
CSRs. CSRs.
@end deffn @end deffn
@deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]... @deffn Command {riscv expose_custom} n0[-m0][,n1[-m1]]...
The RISC-V Debug Specification allows targets to expose custom registers The RISC-V Debug Specification allows targets to expose custom registers
through abstract commands. (See Section 3.5.1.1 in that document.) This command through abstract commands. (See Section 3.5.1.1 in that document.) This command
configures a list of inclusive ranges of those registers to expose. Number 0 configures a list of inclusive ranges of those registers to expose. Number 0