Merge pull request #1101 from en-sc/en-sc/ref-reg-examine
target/riscv: reg cache entry is initialized before access
This commit is contained in:
Evgeniy Naydanov
GitHub
commit
e4d6885eb5
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@ -38,7 +38,9 @@ static const struct reg_arch_type *riscv011_gdb_regno_reg_type(uint32_t regno)
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static int riscv011_init_reg(struct target *target, uint32_t regno)
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{
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return riscv_reg_impl_init_one(target, regno, riscv011_gdb_regno_reg_type(regno));
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return riscv_reg_impl_init_cache_entry(target, regno,
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riscv_reg_impl_gdb_regno_exist(target, regno),
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riscv011_gdb_regno_reg_type(regno));
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}
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int riscv011_reg_init_all(struct target *target)
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@ -727,7 +727,7 @@ clear_cmderr:
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return res;
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}
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static int execute_abstract_command(struct target *target, uint32_t command,
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int riscv013_execute_abstract_command(struct target *target, uint32_t command,
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uint32_t *cmderr)
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{
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assert(cmderr);
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@ -863,7 +863,7 @@ static int write_abstract_arg(struct target *target, unsigned index,
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/**
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* @par size in bits
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*/
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static uint32_t access_register_command(struct target *target, uint32_t number,
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uint32_t riscv013_access_register_command(struct target *target, uint32_t number,
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unsigned size, uint32_t flags)
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{
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uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
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@ -920,11 +920,11 @@ static int register_read_abstract_with_size(struct target *target,
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if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31)
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return ERROR_FAIL;
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uint32_t command = access_register_command(target, number, size,
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uint32_t command = riscv013_access_register_command(target, number, size,
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AC_ACCESS_REGISTER_TRANSFER);
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uint32_t cmderr;
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int result = execute_abstract_command(target, command, &cmderr);
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int result = riscv013_execute_abstract_command(target, command, &cmderr);
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if (result != ERROR_OK) {
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if (cmderr == CMDERR_NOT_SUPPORTED) {
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if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
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@ -969,7 +969,7 @@ static int register_write_abstract(struct target *target, enum gdb_regno number,
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return ERROR_FAIL;
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const unsigned int size_bits = register_size(target, number);
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const uint32_t command = access_register_command(target, number, size_bits,
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const uint32_t command = riscv013_access_register_command(target, number, size_bits,
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AC_ACCESS_REGISTER_TRANSFER |
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AC_ACCESS_REGISTER_WRITE);
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LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
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@ -2112,70 +2112,9 @@ static int examine(struct target *target)
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* program buffer. */
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r->progbuf_size = info->progbufsize;
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result = register_read_abstract_with_size(target, NULL, GDB_REGNO_S0, 64);
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if (result == ERROR_OK)
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r->xlen = 64;
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else
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r->xlen = 32;
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/* Save s0 and s1. The register cache hasn't be initialized yet so we
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* need to take care of this manually. */
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uint64_t s0, s1;
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if (register_read_abstract(target, &s0, GDB_REGNO_S0) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Fatal: Failed to read s0.");
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return ERROR_FAIL;
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}
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if (register_read_abstract(target, &s1, GDB_REGNO_S1) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Fatal: Failed to read s1.");
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return ERROR_FAIL;
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}
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if (register_read_direct(target, &r->misa, GDB_REGNO_MISA)) {
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LOG_TARGET_ERROR(target, "Fatal: Failed to read MISA.");
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return ERROR_FAIL;
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}
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uint64_t value;
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if (register_read_direct(target, &value, GDB_REGNO_VLENB) != ERROR_OK) {
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if (riscv_supports_extension(target, 'V'))
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LOG_TARGET_WARNING(target, "Couldn't read vlenb; vector register access won't work.");
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r->vlenb = 0;
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} else {
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r->vlenb = value;
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LOG_TARGET_INFO(target, "Vector support with vlenb=%d", r->vlenb);
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}
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if (register_read_direct(target, &value, GDB_REGNO_MTOPI) == ERROR_OK) {
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r->mtopi_readable = true;
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if (register_read_direct(target, &value, GDB_REGNO_MTOPEI) == ERROR_OK) {
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LOG_TARGET_INFO(target, "S?aia detected with IMSIC");
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r->mtopei_readable = true;
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} else {
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r->mtopei_readable = false;
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LOG_TARGET_INFO(target, "S?aia detected without IMSIC");
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}
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} else {
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r->mtopi_readable = false;
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}
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/* Display this as early as possible to help people who are using
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* really slow simulators. */
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LOG_TARGET_DEBUG(target, " XLEN=%d, misa=0x%" PRIx64, r->xlen, r->misa);
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/* Restore s0 and s1. */
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if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Fatal: Failed to write back s0.");
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return ERROR_FAIL;
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}
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if (register_write_direct(target, GDB_REGNO_S1, s1) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Fatal: Failed to write back s1.");
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return ERROR_FAIL;
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}
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/* Now init registers based on what we discovered. */
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if (riscv013_reg_init_all(target) != ERROR_OK)
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return ERROR_FAIL;
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result = riscv013_reg_examine_all(target);
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if (result != ERROR_OK)
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return result;
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if (set_dcsr_ebreak(target, false) != ERROR_OK)
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return ERROR_FAIL;
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@ -3651,7 +3590,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
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/* Execute the command */
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uint32_t cmderr;
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result = execute_abstract_command(target, command, &cmderr);
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result = riscv013_execute_abstract_command(target, command, &cmderr);
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/* TODO: we need to modify error handling here. */
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/* NOTE: in case of timeout cmderr is set to CMDERR_NONE */
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@ -3673,7 +3612,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
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} else {
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/* Try the same access but with postincrement disabled. */
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command = access_memory_command(target, false, width, false, false);
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result = execute_abstract_command(target, command, &cmderr);
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result = riscv013_execute_abstract_command(target, command, &cmderr);
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if (result == ERROR_OK) {
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LOG_TARGET_DEBUG(target, "aampostincrement is not supported on this target.");
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info->has_aampostincrement = YNM_NO;
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@ -3744,7 +3683,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
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/* Execute the command */
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uint32_t cmderr;
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result = execute_abstract_command(target, command, &cmderr);
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result = riscv013_execute_abstract_command(target, command, &cmderr);
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/* TODO: we need to modify error handling here. */
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/* NOTE: in case of timeout cmderr is set to CMDERR_NONE */
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@ -3766,7 +3705,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
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} else {
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/* Try the same access but with postincrement disabled. */
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command = access_memory_command(target, false, width, false, true);
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result = execute_abstract_command(target, command, &cmderr);
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result = riscv013_execute_abstract_command(target, command, &cmderr);
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if (result == ERROR_OK) {
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LOG_TARGET_DEBUG(target, "aampostincrement is not supported on this target.");
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info->has_aampostincrement = YNM_NO;
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@ -3812,11 +3751,11 @@ static int read_memory_progbuf_inner_startup(struct target *target,
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/* AC_ACCESS_REGISTER_POSTEXEC is used to trigger first stage of the
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* pipeline (memory -> s1) whenever this command is executed.
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*/
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const uint32_t startup_command = access_register_command(target,
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const uint32_t startup_command = riscv013_access_register_command(target,
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GDB_REGNO_S1, riscv_xlen(target),
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AC_ACCESS_REGISTER_TRANSFER | AC_ACCESS_REGISTER_POSTEXEC);
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uint32_t cmderr;
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if (execute_abstract_command(target, startup_command, &cmderr) != ERROR_OK)
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if (riscv013_execute_abstract_command(target, startup_command, &cmderr) != ERROR_OK)
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return ERROR_FAIL;
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/* TODO: we need to modify error handling here. */
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/* NOTE: in case of timeout cmderr is set to CMDERR_NONE */
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@ -4299,11 +4238,11 @@ static int read_memory_progbuf_inner_one(struct target *target,
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if (write_abstract_arg(target, 0, access.target_address, riscv_xlen(target))
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!= ERROR_OK)
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return ERROR_FAIL;
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uint32_t command = access_register_command(target, GDB_REGNO_S1,
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uint32_t command = riscv013_access_register_command(target, GDB_REGNO_S1,
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riscv_xlen(target), AC_ACCESS_REGISTER_WRITE |
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AC_ACCESS_REGISTER_TRANSFER | AC_ACCESS_REGISTER_POSTEXEC);
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uint32_t cmderr;
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if (execute_abstract_command(target, command, &cmderr) != ERROR_OK)
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if (riscv013_execute_abstract_command(target, command, &cmderr) != ERROR_OK)
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return ERROR_FAIL;
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return read_word_from_s1(target, access, 0);
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@ -4642,14 +4581,14 @@ static int write_memory_progbuf_startup(struct target *target, target_addr_t *ad
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/* Write and execute command that moves the value from data0 [, data1]
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* into S1 and executes program buffer. */
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uint32_t command = access_register_command(target,
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uint32_t command = riscv013_access_register_command(target,
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GDB_REGNO_S1, riscv_xlen(target),
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AC_ACCESS_REGISTER_POSTEXEC |
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AC_ACCESS_REGISTER_TRANSFER |
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AC_ACCESS_REGISTER_WRITE);
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uint32_t cmderr;
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if (execute_abstract_command(target, command, &cmderr) != ERROR_OK)
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if (riscv013_execute_abstract_command(target, command, &cmderr) != ERROR_OK)
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return ERROR_FAIL;
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log_memory_access64(*address_p, value, size, /*is_read*/ false);
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@ -5320,7 +5259,7 @@ static int riscv013_execute_progbuf(struct target *target, uint32_t *cmderr)
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run_program = set_field(run_program, AC_ACCESS_REGISTER_TRANSFER, 0);
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run_program = set_field(run_program, AC_ACCESS_REGISTER_REGNO, 0x1000);
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return execute_abstract_command(target, run_program, cmderr);
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return riscv013_execute_abstract_command(target, run_program, cmderr);
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}
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static void riscv013_fill_dmi_write(struct target *target, char *buf, uint64_t a, uint32_t d)
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@ -19,5 +19,9 @@ int riscv013_set_register(struct target *target, enum gdb_regno rid,
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riscv_reg_t value);
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int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
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const uint8_t *value);
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uint32_t riscv013_access_register_command(struct target *target, uint32_t number,
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unsigned int size, uint32_t flags);
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int riscv013_execute_abstract_command(struct target *target, uint32_t command,
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uint32_t *cmderr);
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#endif /* OPENOCD_TARGET_RISCV_RISCV_013_H */
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@ -9,6 +9,7 @@
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#include "riscv_reg.h"
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#include "riscv_reg_impl.h"
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#include "riscv-013.h"
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#include "debug_defines.h"
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#include <helper/time_support.h>
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static int riscv013_reg_get(struct reg *reg)
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@ -85,33 +86,196 @@ static int riscv013_reg_set(struct reg *reg, uint8_t *buf)
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static const struct reg_arch_type *riscv013_gdb_regno_reg_type(uint32_t regno)
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{
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static const struct reg_arch_type riscv011_reg_type = {
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static const struct reg_arch_type riscv013_reg_type = {
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.get = riscv013_reg_get,
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.set = riscv013_reg_set
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};
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return &riscv011_reg_type;
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return &riscv013_reg_type;
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}
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static int riscv013_init_reg(struct target *target, uint32_t regno)
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static int init_cache_entry(struct target *target, uint32_t regno)
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{
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return riscv_reg_impl_init_one(target, regno, riscv013_gdb_regno_reg_type(regno));
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struct reg * const reg = riscv_reg_impl_cache_entry(target, regno);
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if (riscv_reg_impl_is_initialized(reg))
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return ERROR_OK;
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return riscv_reg_impl_init_cache_entry(target, regno,
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riscv_reg_impl_gdb_regno_exist(target, regno),
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riscv013_gdb_regno_reg_type(regno));
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}
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int riscv013_reg_init_all(struct target *target)
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/**
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* Some registers are optional (e.g. "misa"). For such registers it is first
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* assumed they exist (via "assume_reg_exist()"), then the read is attempted
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* (via the usual "riscv_reg_get()") and if the read fails, the register is
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* marked as non-existing (via "riscv_reg_impl_set_exist()").
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*/
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static int assume_reg_exist(struct target *target, uint32_t regno)
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{
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if (riscv_reg_impl_init_cache(target) != ERROR_OK)
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return riscv_reg_impl_init_cache_entry(target, regno,
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/* exist */ true, riscv013_gdb_regno_reg_type(regno));
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}
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static int examine_xlen(struct target *target)
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{
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RISCV_INFO(r);
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unsigned int cmderr;
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const uint32_t command = riscv013_access_register_command(target,
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GDB_REGNO_S0, /* size */ 64, AC_ACCESS_REGISTER_TRANSFER);
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int res = riscv013_execute_abstract_command(target, command, &cmderr);
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if (res == ERROR_OK) {
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r->xlen = 64;
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return ERROR_OK;
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}
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if (res == ERROR_TIMEOUT_REACHED)
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return ERROR_FAIL;
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r->xlen = 32;
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return ERROR_OK;
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}
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static int examine_vlenb(struct target *target)
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{
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RISCV_INFO(r);
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/* Reading "vlenb" requires "mstatus.vs" to be set, so "mstatus" should
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* be accessible.*/
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int res = init_cache_entry(target, GDB_REGNO_MSTATUS);
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if (res != ERROR_OK)
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return res;
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res = assume_reg_exist(target, GDB_REGNO_VLENB);
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if (res != ERROR_OK)
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return res;
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riscv_reg_t vlenb_val;
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if (riscv_reg_get(target, &vlenb_val, GDB_REGNO_VLENB) != ERROR_OK) {
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if (riscv_supports_extension(target, 'V'))
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LOG_TARGET_WARNING(target, "Couldn't read vlenb; vector register access won't work.");
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r->vlenb = 0;
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return riscv_reg_impl_set_exist(target, GDB_REGNO_VLENB, false);
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}
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/* As defined by RISC-V V extension specification:
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* https://github.com/riscv/riscv-v-spec/blob/2f68ef7256d6ec53e4d2bd7cb12862f406d64e34/v-spec.adoc?plain=1#L67-L72 */
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const unsigned int vlen_max = 65536;
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const unsigned int vlenb_max = vlen_max / 8;
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if (vlenb_val > vlenb_max) {
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LOG_TARGET_WARNING(target, "'vlenb == %" PRIu64
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"' is greater than maximum allowed by specification (%u); vector register access won't work.",
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vlenb_val, vlenb_max);
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r->vlenb = 0;
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return ERROR_OK;
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}
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assert(vlenb_max <= UINT_MAX);
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r->vlenb = (unsigned int)vlenb_val;
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LOG_TARGET_INFO(target, "Vector support with vlenb=%u", r->vlenb);
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return ERROR_OK;
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}
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static int examine_misa(struct target *target)
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{
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RISCV_INFO(r);
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int res = init_cache_entry(target, GDB_REGNO_MISA);
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if (res != ERROR_OK)
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return res;
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res = riscv_reg_get(target, &r->misa, GDB_REGNO_MISA);
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if (res != ERROR_OK)
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return res;
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return ERROR_OK;
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}
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static int examine_mtopi(struct target *target)
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{
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RISCV_INFO(r);
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/* Assume the registers exist */
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r->mtopi_readable = true;
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r->mtopei_readable = true;
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int res = assume_reg_exist(target, GDB_REGNO_MTOPI);
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if (res != ERROR_OK)
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return res;
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res = assume_reg_exist(target, GDB_REGNO_MTOPEI);
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if (res != ERROR_OK)
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return res;
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riscv_reg_t value;
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if (riscv_reg_get(target, &value, GDB_REGNO_MTOPI) != ERROR_OK) {
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r->mtopi_readable = false;
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r->mtopei_readable = false;
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} else if (riscv_reg_get(target, &value, GDB_REGNO_MTOPEI) != ERROR_OK) {
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LOG_TARGET_INFO(target, "S?aia detected without IMSIC");
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r->mtopei_readable = false;
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} else {
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LOG_TARGET_INFO(target, "S?aia detected with IMSIC");
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}
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res = riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPI, r->mtopi_readable);
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if (res != ERROR_OK)
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return res;
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||||
return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, r->mtopei_readable);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function assumes target's DM to be initialized (target is able to
|
||||
* access DMs registers, execute program buffer, etc.)
|
||||
*/
|
||||
int riscv013_reg_examine_all(struct target *target)
|
||||
{
|
||||
RISCV_INFO(r);
|
||||
|
||||
int res = riscv_reg_impl_init_cache(target);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
init_shared_reg_info(target);
|
||||
|
||||
assert(target->state == TARGET_HALTED);
|
||||
|
||||
res = examine_xlen(target);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
/* Reading CSRs may clobber "s0", "s1", so it should be possible to
|
||||
* save them in cache. */
|
||||
res = init_cache_entry(target, GDB_REGNO_S0);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
res = init_cache_entry(target, GDB_REGNO_S1);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
res = examine_misa(target);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
/* Display this as early as possible to help people who are using
|
||||
* really slow simulators. */
|
||||
LOG_TARGET_DEBUG(target, " XLEN=%d, misa=0x%" PRIx64, riscv_xlen(target), r->misa);
|
||||
|
||||
res = examine_vlenb(target);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
riscv_reg_impl_init_vector_reg_type(target);
|
||||
|
||||
for (uint32_t regno = 0; regno < target->reg_cache->num_regs; ++regno)
|
||||
if (riscv013_init_reg(target, regno) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
res = examine_mtopi(target);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
if (riscv_reg_impl_expose_csrs(target) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
for (uint32_t regno = 0; regno < target->reg_cache->num_regs; ++regno) {
|
||||
res = init_cache_entry(target, regno);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
|
||||
res = riscv_reg_impl_expose_csrs(target);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
|
||||
riscv_reg_impl_hide_csrs(target);
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,11 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* Init initialize register cache. After this function all registers can be
|
||||
* safely accessed via functions described here and in `riscv_reg.h`.
|
||||
* This function assumes target is halted.
|
||||
* After this function all registers can be safely accessed via functions
|
||||
* described here and in `riscv_reg.h`.
|
||||
*/
|
||||
int riscv013_reg_init_all(struct target *target);
|
||||
int riscv013_reg_examine_all(struct target *target);
|
||||
|
||||
/**
|
||||
* This function is used to save the value of a register in cache. The register
|
||||
|
|
|
|||
|
|
@ -376,8 +376,19 @@ static bool is_known_standard_csr(unsigned int csr_num)
|
|||
return is_csr_in_buf[csr_num];
|
||||
}
|
||||
|
||||
static bool gdb_regno_exist(const struct target *target, uint32_t regno)
|
||||
bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno)
|
||||
{
|
||||
switch (regno) {
|
||||
case GDB_REGNO_VLENB:
|
||||
case GDB_REGNO_MTOPI:
|
||||
case GDB_REGNO_MTOPEI:
|
||||
assert(false
|
||||
&& "Existence of other registers is determined "
|
||||
"depending on existence of these ones, so "
|
||||
"whether these register exist or not should be "
|
||||
"set explicitly.");
|
||||
};
|
||||
|
||||
if (regno <= GDB_REGNO_XPR15 ||
|
||||
regno == GDB_REGNO_PC ||
|
||||
regno == GDB_REGNO_PRIV)
|
||||
|
|
@ -403,7 +414,6 @@ static bool gdb_regno_exist(const struct target *target, uint32_t regno)
|
|||
case CSR_VL:
|
||||
case CSR_VCSR:
|
||||
case CSR_VTYPE:
|
||||
case CSR_VLENB:
|
||||
return vlenb_exists(target);
|
||||
case CSR_SCOUNTEREN:
|
||||
case CSR_SSTATUS:
|
||||
|
|
@ -599,14 +609,15 @@ static int resize_reg(const struct target *target, uint32_t regno, bool exist,
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int set_reg_exist(const struct target *target, uint32_t regno, bool exist)
|
||||
int riscv_reg_impl_set_exist(const struct target *target, uint32_t regno, bool exist)
|
||||
{
|
||||
const struct reg *reg = riscv_reg_impl_cache_entry(target, regno);
|
||||
assert(riscv_reg_impl_is_initialized(reg));
|
||||
return resize_reg(target, regno, exist, reg->size);
|
||||
}
|
||||
|
||||
int riscv_reg_impl_init_one(struct target *target, uint32_t regno, const struct reg_arch_type *reg_type)
|
||||
int riscv_reg_impl_init_cache_entry(struct target *target, uint32_t regno,
|
||||
bool exist, const struct reg_arch_type *reg_type)
|
||||
{
|
||||
struct reg * const reg = riscv_reg_impl_cache_entry(target, regno);
|
||||
if (riscv_reg_impl_is_initialized(reg))
|
||||
|
|
@ -634,8 +645,7 @@ int riscv_reg_impl_init_one(struct target *target, uint32_t regno, const struct
|
|||
reg_arch_info->target = target;
|
||||
reg_arch_info->custom_number = gdb_regno_custom_number(target, regno);
|
||||
}
|
||||
return resize_reg(target, regno, gdb_regno_exist(target, regno),
|
||||
gdb_regno_size(target, regno));
|
||||
return resize_reg(target, regno, exist, gdb_regno_size(target, regno));
|
||||
}
|
||||
|
||||
static int init_custom_register_names(struct list_head *expose_custom,
|
||||
|
|
@ -725,7 +735,7 @@ int riscv_reg_impl_expose_csrs(const struct target *target)
|
|||
csr_number);
|
||||
continue;
|
||||
}
|
||||
if (set_reg_exist(target, regno, /*exist*/ true) != ERROR_OK)
|
||||
if (riscv_reg_impl_set_exist(target, regno, /*exist*/ true) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
LOG_TARGET_DEBUG(target, "Exposing additional CSR %d (name=%s)",
|
||||
csr_number, reg->name);
|
||||
|
|
@ -834,15 +844,8 @@ static int riscv_set_or_write_register(struct target *target,
|
|||
return riscv_set_or_write_register(target, GDB_REGNO_DCSR, dcsr, write_through);
|
||||
}
|
||||
|
||||
if (!target->reg_cache) {
|
||||
assert(!target_was_examined(target));
|
||||
LOG_TARGET_DEBUG(target,
|
||||
"No cache, writing to target: %s <- 0x%" PRIx64,
|
||||
riscv_reg_gdb_regno_name(target, regid), value);
|
||||
return riscv013_set_register(target, regid, value);
|
||||
}
|
||||
|
||||
struct reg *reg = riscv_reg_impl_cache_entry(target, regid);
|
||||
assert(riscv_reg_impl_is_initialized(reg));
|
||||
|
||||
if (!reg->exist) {
|
||||
LOG_TARGET_DEBUG(target, "Register %s does not exist.", reg->name);
|
||||
|
|
@ -935,21 +938,15 @@ int riscv_reg_get(struct target *target, riscv_reg_t *value,
|
|||
RISCV_INFO(r);
|
||||
assert(r);
|
||||
if (r->dtm_version == DTM_DTMCS_VERSION_0_11)
|
||||
return riscv013_get_register(target, value, regid);
|
||||
return riscv011_get_register(target, value, regid);
|
||||
|
||||
keep_alive();
|
||||
|
||||
if (regid == GDB_REGNO_PC)
|
||||
return riscv_reg_get(target, value, GDB_REGNO_DPC);
|
||||
|
||||
if (!target->reg_cache) {
|
||||
assert(!target_was_examined(target));
|
||||
LOG_TARGET_DEBUG(target, "No cache, reading %s from target",
|
||||
riscv_reg_gdb_regno_name(target, regid));
|
||||
return riscv013_get_register(target, value, regid);
|
||||
}
|
||||
|
||||
struct reg *reg = riscv_reg_impl_cache_entry(target, regid);
|
||||
assert(riscv_reg_impl_is_initialized(reg));
|
||||
if (!reg->exist) {
|
||||
LOG_TARGET_DEBUG(target, "Register %s does not exist.", reg->name);
|
||||
return ERROR_FAIL;
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
* This file describes the helpers to use during register cache initialization
|
||||
* of a RISC-V target. Each cache entry proceedes through the following stages:
|
||||
* - not allocated before `riscv_reg_impl_init_cache()`
|
||||
* - not initialized before the call to `riscv_reg_impl_init_one()` with appropriate regno.
|
||||
* - not initialized before the call to `riscv_reg_impl_init_cache_entry()` with appropriate regno.
|
||||
* - initialized until `riscv_reg_free_all()` is called.
|
||||
*/
|
||||
static inline bool riscv_reg_impl_is_initialized(const struct reg *reg)
|
||||
|
|
@ -37,8 +37,18 @@ static inline bool riscv_reg_impl_is_initialized(const struct reg *reg)
|
|||
int riscv_reg_impl_init_cache(struct target *target);
|
||||
|
||||
/** Initialize register. */
|
||||
int riscv_reg_impl_init_one(struct target *target, uint32_t regno,
|
||||
const struct reg_arch_type *reg_type);
|
||||
int riscv_reg_impl_init_cache_entry(struct target *target, uint32_t regno,
|
||||
bool exist, const struct reg_arch_type *reg_type);
|
||||
|
||||
/**
|
||||
* For most registers, returns whether they exist or not.
|
||||
* For some registers the "exist" bit should be set explicitly.
|
||||
*/
|
||||
bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno);
|
||||
|
||||
/** Mark register as existing or not. */
|
||||
int riscv_reg_impl_set_exist(const struct target *target,
|
||||
uint32_t regno, bool exist);
|
||||
|
||||
/** Return the entry in the register cache of the target. */
|
||||
struct reg *riscv_reg_impl_cache_entry(const struct target *target,
|
||||
|
|
|
|||
Loading…
Reference in New Issue