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flash/nor/nrf5: do not check FICR PPFC on nRF52 

Change-Id: I6beee9b85a542040f2495513b5ba51bd8e1389db
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4867
Tested-by: jenkins
This commit is contained in:
Tomas Vanek 2019-01-21 14:44:45 +01:00
parent 882df85ec1
commit e2ca8914f2
1 changed files with 28 additions and 25 deletions
src/flash/nor
nrf5.c

5
src/flash/nor/nrf5.c
View File

@ -817,6 +817,7 @@ static int nrf5_erase_page(struct flash_bank *bank,
} }
if (bank->base == NRF5_UICR_BASE) { if (bank->base == NRF5_UICR_BASE) {
if (chip->features & NRF5_FEATURE_SERIES_51) {
uint32_t ppfc; uint32_t ppfc;
res = target_read_u32(chip->target, NRF51_FICR_PPFC, res = target_read_u32(chip->target, NRF51_FICR_PPFC,
&ppfc); &ppfc);
@ -835,6 +836,7 @@ static int nrf5_erase_page(struct flash_bank *bank,
LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region"); LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
return ERROR_FAIL; return ERROR_FAIL;
} }
}
res = nrf5_nvmc_generic_erase(chip, res = nrf5_nvmc_generic_erase(chip,
NRF5_NVMC_ERASEUICR, NRF5_NVMC_ERASEUICR,
@ -1077,8 +1079,8 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
if (res != ERROR_OK) if (res != ERROR_OK)
return res; return res;
if (chip->features & NRF5_FEATURE_SERIES_51) {
uint32_t ppfc; uint32_t ppfc;
res = target_read_u32(target, NRF51_FICR_PPFC, res = target_read_u32(target, NRF51_FICR_PPFC,
&ppfc); &ppfc);
if (res != ERROR_OK) { if (res != ERROR_OK) {
@ -1091,6 +1093,7 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
"mass erase command won't work."); "mass erase command won't work.");
return ERROR_FAIL; return ERROR_FAIL;
} }
}
res = nrf5_erase_all(chip); res = nrf5_erase_all(chip);
if (res != ERROR_OK) { if (res != ERROR_OK) {