flash/nor/nrf5: rename registers by nRF series
Change-Id: I70af671c52665b27a28508e06e7d3e5e40a621f7 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4866 Tested-by: jenkins
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@ -39,13 +39,15 @@ enum nrf5_ficr_registers {
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NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
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NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
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NRF5_FICR_CLENR0 = NRF5_FICR_REG(0x028),
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NRF5_FICR_PPFC = NRF5_FICR_REG(0x02C),
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NRF5_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
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NRF5_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
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NRF5_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
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NRF5_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
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NRF5_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
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NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
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NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
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NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
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NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
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NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
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NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
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NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
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NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
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NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
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NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
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@ -60,17 +62,18 @@ enum nrf5_ficr_registers {
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NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
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NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
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NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
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NRF5_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
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NRF5_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
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NRF5_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
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NRF5_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
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NRF5_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
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NRF5_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
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NRF5_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
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NRF5_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
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NRF5_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
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NRF5_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
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NRF5_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
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NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
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NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
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NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
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NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
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NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
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NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
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NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
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NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
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NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
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NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
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NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
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/* Following registers are available on nRF52 and on nRF51 since rev 3 */
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NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
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@ -86,10 +89,10 @@ enum nrf5_uicr_registers {
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#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
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NRF5_UICR_CLENR0 = NRF5_UICR_REG(0x000),
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NRF5_UICR_RBPCONF = NRF5_UICR_REG(0x004),
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NRF5_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
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NRF5_UICR_FWID = NRF5_UICR_REG(0x010),
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NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
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NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
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NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
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NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
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};
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enum nrf5_nvmc_registers {
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@ -479,7 +482,7 @@ static int nrf5_protect_check(struct flash_bank *bank)
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return ERROR_FLASH_OPER_UNSUPPORTED;
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}
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res = target_read_u32(chip->target, NRF5_FICR_CLENR0,
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res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
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&clenr0);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code region 0 size[FICR]");
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@ -487,7 +490,7 @@ static int nrf5_protect_check(struct flash_bank *bank)
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}
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if (clenr0 == 0xFFFFFFFF) {
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res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
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res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
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&clenr0);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code region 0 size[UICR]");
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@ -526,7 +529,7 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
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return ERROR_FAIL;
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}
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res = target_read_u32(chip->target, NRF5_FICR_PPFC,
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res = target_read_u32(chip->target, NRF51_FICR_PPFC,
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&ppfc);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read PPFC register");
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@ -538,7 +541,7 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
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return ERROR_FAIL;
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}
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res = target_read_u32(chip->target, NRF5_UICR_CLENR0,
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res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
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&clenr0);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read code region 0 size[UICR]");
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@ -546,7 +549,7 @@ static int nrf5_protect(struct flash_bank *bank, int set, int first, int last)
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}
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if (clenr0 == 0xFFFFFFFF) {
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res = target_write_u32(chip->target, NRF5_UICR_CLENR0,
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res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
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clenr0);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't write code region 0 size[UICR]");
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@ -815,7 +818,7 @@ static int nrf5_erase_page(struct flash_bank *bank,
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if (bank->base == NRF5_UICR_BASE) {
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uint32_t ppfc;
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res = target_read_u32(chip->target, NRF5_FICR_PPFC,
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res = target_read_u32(chip->target, NRF51_FICR_PPFC,
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&ppfc);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read PPFC register");
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@ -1076,7 +1079,7 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
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uint32_t ppfc;
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res = target_read_u32(target, NRF5_FICR_PPFC,
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res = target_read_u32(target, NRF51_FICR_PPFC,
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&ppfc);
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if (res != ERROR_OK) {
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LOG_ERROR("Couldn't read PPFC register");
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@ -1133,13 +1136,13 @@ COMMAND_HANDLER(nrf5_handle_info_command)
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} ficr[] = {
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{ .address = NRF5_FICR_CODEPAGESIZE },
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{ .address = NRF5_FICR_CODESIZE },
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{ .address = NRF5_FICR_CLENR0 },
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{ .address = NRF5_FICR_PPFC },
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{ .address = NRF5_FICR_NUMRAMBLOCK },
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{ .address = NRF5_FICR_SIZERAMBLOCK0 },
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{ .address = NRF5_FICR_SIZERAMBLOCK1 },
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{ .address = NRF5_FICR_SIZERAMBLOCK2 },
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{ .address = NRF5_FICR_SIZERAMBLOCK3 },
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{ .address = NRF51_FICR_CLENR0 },
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{ .address = NRF51_FICR_PPFC },
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{ .address = NRF51_FICR_NUMRAMBLOCK },
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{ .address = NRF51_FICR_SIZERAMBLOCK0 },
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{ .address = NRF51_FICR_SIZERAMBLOCK1 },
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{ .address = NRF51_FICR_SIZERAMBLOCK2 },
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{ .address = NRF51_FICR_SIZERAMBLOCK3 },
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{ .address = NRF5_FICR_CONFIGID },
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{ .address = NRF5_FICR_DEVICEID0 },
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{ .address = NRF5_FICR_DEVICEID1 },
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@ -1154,22 +1157,22 @@ COMMAND_HANDLER(nrf5_handle_info_command)
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{ .address = NRF5_FICR_DEVICEADDRTYPE },
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{ .address = NRF5_FICR_DEVICEADDR0 },
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{ .address = NRF5_FICR_DEVICEADDR1 },
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{ .address = NRF5_FICR_OVERRIDEN },
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{ .address = NRF5_FICR_NRF_1MBIT0 },
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{ .address = NRF5_FICR_NRF_1MBIT1 },
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{ .address = NRF5_FICR_NRF_1MBIT2 },
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{ .address = NRF5_FICR_NRF_1MBIT3 },
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{ .address = NRF5_FICR_NRF_1MBIT4 },
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{ .address = NRF5_FICR_BLE_1MBIT0 },
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{ .address = NRF5_FICR_BLE_1MBIT1 },
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{ .address = NRF5_FICR_BLE_1MBIT2 },
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{ .address = NRF5_FICR_BLE_1MBIT3 },
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{ .address = NRF5_FICR_BLE_1MBIT4 },
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{ .address = NRF51_FICR_OVERRIDEN },
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{ .address = NRF51_FICR_NRF_1MBIT0 },
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{ .address = NRF51_FICR_NRF_1MBIT1 },
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{ .address = NRF51_FICR_NRF_1MBIT2 },
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{ .address = NRF51_FICR_NRF_1MBIT3 },
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{ .address = NRF51_FICR_NRF_1MBIT4 },
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{ .address = NRF51_FICR_BLE_1MBIT0 },
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{ .address = NRF51_FICR_BLE_1MBIT1 },
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{ .address = NRF51_FICR_BLE_1MBIT2 },
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{ .address = NRF51_FICR_BLE_1MBIT3 },
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{ .address = NRF51_FICR_BLE_1MBIT4 },
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}, uicr[] = {
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{ .address = NRF5_UICR_CLENR0, },
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{ .address = NRF5_UICR_RBPCONF },
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{ .address = NRF5_UICR_XTALFREQ },
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{ .address = NRF5_UICR_FWID },
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{ .address = NRF51_UICR_CLENR0, },
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{ .address = NRF51_UICR_RBPCONF },
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{ .address = NRF51_UICR_XTALFREQ },
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{ .address = NRF51_UICR_FWID },
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};
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for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
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