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rtos/nuttx: add riscv stacking info 

Tested with Espressif ESP32-C3 MCU

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ia71ace4909f2dc93ddc07a2ec5524cf374f1937c
Reviewed-on: https://review.openocd.org/c/openocd/+/7251
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas 2022-10-05 18:38:23 +02:00 committed by Antonio Borneo
parent 463df95215
commit dfbbfac4d7
2 changed files with 47 additions and 0 deletions
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46
src/rtos/rtos_nuttx_stackings.c
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@ -7,6 +7,8 @@
#include "rtos.h" #include "rtos.h"
#include "target/armv7m.h" #include "target/armv7m.h"
#include "rtos_nuttx_stackings.h" #include "rtos_nuttx_stackings.h"
#include "rtos_standard_stackings.h"
#include <target/riscv/riscv.h>
/* see arch/arm/include/armv7-m/irq_cmnvector.h */ /* see arch/arm/include/armv7-m/irq_cmnvector.h */
static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = { static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = {
@ -62,3 +64,47 @@ const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {
.num_output_registers = 17, .num_output_registers = 17,
.register_offsets = nuttx_stack_offsets_cortex_m_fpu, .register_offsets = nuttx_stack_offsets_cortex_m_fpu,
}; };
static const struct stack_register_offset nuttx_stack_offsets_riscv[] = {
{ GDB_REGNO_ZERO, -1, 32 },
{ GDB_REGNO_RA, 0x04, 32 },
{ GDB_REGNO_SP, 0x08, 32 },
{ GDB_REGNO_GP, 0x0c, 32 },
{ GDB_REGNO_TP, 0x10, 32 },
{ GDB_REGNO_T0, 0x14, 32 },
{ GDB_REGNO_T1, 0x18, 32 },
{ GDB_REGNO_T2, 0x1c, 32 },
{ GDB_REGNO_FP, 0x20, 32 },
{ GDB_REGNO_S1, 0x24, 32 },
{ GDB_REGNO_A0, 0x28, 32 },
{ GDB_REGNO_A1, 0x2c, 32 },
{ GDB_REGNO_A2, 0x30, 32 },
{ GDB_REGNO_A3, 0x34, 32 },
{ GDB_REGNO_A4, 0x38, 32 },
{ GDB_REGNO_A5, 0x3c, 32 },
{ GDB_REGNO_A6, 0x40, 32 },
{ GDB_REGNO_A7, 0x44, 32 },
{ GDB_REGNO_S2, 0x48, 32 },
{ GDB_REGNO_S3, 0x4c, 32 },
{ GDB_REGNO_S4, 0x50, 32 },
{ GDB_REGNO_S5, 0x54, 32 },
{ GDB_REGNO_S6, 0x58, 32 },
{ GDB_REGNO_S7, 0x5c, 32 },
{ GDB_REGNO_S8, 0x60, 32 },
{ GDB_REGNO_S9, 0x64, 32 },
{ GDB_REGNO_S10, 0x68, 32 },
{ GDB_REGNO_S11, 0x6c, 32 },
{ GDB_REGNO_T3, 0x70, 32 },
{ GDB_REGNO_T4, 0x74, 32 },
{ GDB_REGNO_T5, 0x78, 32 },
{ GDB_REGNO_T6, 0x7c, 32 },
{ GDB_REGNO_PC, 0x00, 32 },
};
const struct rtos_register_stacking nuttx_riscv_stacking = {
.stack_registers_size = 33 * 4,
.stack_growth_direction = -1,
.num_output_registers = 33,
.calculate_process_stack = rtos_generic_stack_align8,
.register_offsets = nuttx_stack_offsets_riscv,
};

1
src/rtos/rtos_nuttx_stackings.h
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@ -7,5 +7,6 @@
extern const struct rtos_register_stacking nuttx_stacking_cortex_m; extern const struct rtos_register_stacking nuttx_stacking_cortex_m;
extern const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu; extern const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu;
extern const struct rtos_register_stacking nuttx_riscv_stacking;
#endif /* INCLUDED_RTOS_NUTTX_STACKINGS_H */ #endif /* INCLUDED_RTOS_NUTTX_STACKINGS_H */