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src/target/riscv:mfp16mode rename to mmisc_ctl1 

Change-Id: Ica701881b96a9fe774de76d7fb22d03c443af0e0
Signed-off-by: wangyanwen <wangyanwen@nucleisys.com>
This commit is contained in:
wangyanwen 2024-11-07 14:18:45 +08:00 committed by Huaqi Fang
parent 6e9854400e
commit dbe10987e1
1 changed files with 2 additions and 2 deletions
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4
src/target/riscv/encoding.h
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@ -3254,7 +3254,7 @@
#define CSR_MSAVEDCAUSE2 0x7dc
#define CSR_MTLB_CTL 0x7dd
#define CSR_MECC_LOCK 0x7de
#define CSR_MFP16MODE 0x7e2
#define CSR_MMISC_CTL1 0x7e2
#define CSR_LSTEPFORC 0x7e9
#define CSR_PUSHMSUBM 0x7eb
#define CSR_MTVT2 0x7ec
@ -5147,7 +5147,7 @@ DECLARE_CSR(msavedcause1, CSR_MSAVEDCAUSE1)
DECLARE_CSR(msavedcause2, CSR_MSAVEDCAUSE2)
DECLARE_CSR(mtlb_ctl, CSR_MTLB_CTL)
DECLARE_CSR(mecc_lock, CSR_MECC_LOCK)
DECLARE_CSR(mfp16mode, CSR_MFP16MODE)
DECLARE_CSR(mmisc_ctl1, CSR_MMISC_CTL1)
DECLARE_CSR(lstepforc, CSR_LSTEPFORC)
DECLARE_CSR(pushmsubm, CSR_PUSHMSUBM)
DECLARE_CSR(mtvt2, CSR_MTVT2)