From dbe10987e11efb4368481c3dadf8926750a9951d Mon Sep 17 00:00:00 2001 From: wangyanwen Date: Thu, 7 Nov 2024 14:18:45 +0800 Subject: [PATCH] src/target/riscv:mfp16mode rename to mmisc_ctl1 Change-Id: Ica701881b96a9fe774de76d7fb22d03c443af0e0 Signed-off-by: wangyanwen --- src/target/riscv/encoding.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h index 401ac944b..81018ece2 100644 --- a/src/target/riscv/encoding.h +++ b/src/target/riscv/encoding.h @@ -3254,7 +3254,7 @@ #define CSR_MSAVEDCAUSE2 0x7dc #define CSR_MTLB_CTL 0x7dd #define CSR_MECC_LOCK 0x7de -#define CSR_MFP16MODE 0x7e2 +#define CSR_MMISC_CTL1 0x7e2 #define CSR_LSTEPFORC 0x7e9 #define CSR_PUSHMSUBM 0x7eb #define CSR_MTVT2 0x7ec @@ -5147,7 +5147,7 @@ DECLARE_CSR(msavedcause1, CSR_MSAVEDCAUSE1) DECLARE_CSR(msavedcause2, CSR_MSAVEDCAUSE2) DECLARE_CSR(mtlb_ctl, CSR_MTLB_CTL) DECLARE_CSR(mecc_lock, CSR_MECC_LOCK) -DECLARE_CSR(mfp16mode, CSR_MFP16MODE) +DECLARE_CSR(mmisc_ctl1, CSR_MMISC_CTL1) DECLARE_CSR(lstepforc, CSR_LSTEPFORC) DECLARE_CSR(pushmsubm, CSR_PUSHMSUBM) DECLARE_CSR(mtvt2, CSR_MTVT2)