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aarch64: reset fixes 

Make sure all core register caches are invalidated on reset
assert, make sure to re-init debug registers on deassert.

Change-Id: I82350d04cc3eaae5e35245d13d6c1fb0a8d59807
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3990
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Matthias Welwarsky 2017-02-15 15:30:21 +01:00 committed by Paul Fertser
parent 6fb9f2e3ee
commit d6535e0ce5
1 changed files with 11 additions and 2 deletions
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13
src/target/aarch64.c
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@ -169,6 +169,13 @@ static int aarch64_init_debug_access(struct target *target)
LOG_DEBUG(" "); LOG_DEBUG(" ");
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_OSLAR, 0);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "oslock");
return retval;
}
/* Clear Sticky Power Down status Bit in PRSR to enable access to /* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */ the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(armv8->debug_ap, retval = mem_ap_read_atomic_u32(armv8->debug_ap,
@ -1256,8 +1263,10 @@ static int aarch64_assert_reset(struct target *target)
} }
/* registers are now invalid */ /* registers are now invalid */
if (target_was_examined(target)) if (target_was_examined(target)) {
register_cache_invalidate(armv8->arm.core_cache); register_cache_invalidate(armv8->arm.core_cache);
register_cache_invalidate(armv8->arm.core_cache->next);
}
target->state = TARGET_RESET; target->state = TARGET_RESET;
@ -1290,7 +1299,7 @@ static int aarch64_deassert_reset(struct target *target)
} }
} }
return ERROR_OK; return aarch64_init_debug_access(target);
} }
static int aarch64_write_apb_ap_memory(struct target *target, static int aarch64_write_apb_ap_memory(struct target *target,