interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Explain what RISC-V targets are supported. 

Change-Id: I4c50a1507ca0fcbdd8340a851e8ab0ae1feca1a2
This commit is contained in:
Tim Newsome 2018-07-17 14:09:55 -07:00
parent 9c6aedac7f
commit bda019bdc2
1 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
doc/openocd.texi
View File

@ -8903,8 +8903,11 @@ Display all registers in @emph{group}.
@section RISC-V Architecture
@uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug
Specification.
debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
harts. (It's possible to increase this limit to 1024 by changing
RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
Debug Specification, but there is also support for legacy targets that
implement version 0.11.
@subsection RISC-V Terminology