From bda019bdc2c56e3a7e231c22b9b55b44f5f7e9c0 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 17 Jul 2018 14:09:55 -0700 Subject: [PATCH] Explain what RISC-V targets are supported. Change-Id: I4c50a1507ca0fcbdd8340a851e8ab0ae1feca1a2 --- doc/openocd.texi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index 7f29fdcee..bf42ab17d 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -8903,8 +8903,11 @@ Display all registers in @emph{group}. @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG -debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug -Specification. +debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32 +harts. (It's possible to increase this limit to 1024 by changing +RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V +Debug Specification, but there is also support for legacy targets that +implement version 0.11. @subsection RISC-V Terminology